mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
synced 2026-01-08 02:00:21 +01:00
nvk: Move Begin/EndTransformFeedback to nvk_cmd_draw.c
There's nothing generic about this so it should go in the 3D-specific file. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26408>
This commit is contained in:
Faith Ekstrand
Marge Bot
parent
d96705e4b8
commit
ee22aa27b5
2 changed files with 146 additions and 145 deletions
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@ -562,148 +562,3 @@ nvk_CmdPushDescriptorSetWithTemplateKHR(VkCommandBuffer commandBuffer,
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nvk_push_descriptor_set_update_template(push_set, set_layout, template,
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pData);
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}
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VKAPI_ATTR void VKAPI_CALL
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nvk_CmdBindTransformFeedbackBuffersEXT(VkCommandBuffer commandBuffer,
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uint32_t firstBinding,
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uint32_t bindingCount,
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const VkBuffer *pBuffers,
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const VkDeviceSize *pOffsets,
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const VkDeviceSize *pSizes)
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{
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VK_FROM_HANDLE(nvk_cmd_buffer, cmd, commandBuffer);
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for (uint32_t i = 0; i < bindingCount; i++) {
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VK_FROM_HANDLE(nvk_buffer, buffer, pBuffers[i]);
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uint32_t idx = firstBinding + i;
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uint64_t size = pSizes ? pSizes[i] : VK_WHOLE_SIZE;
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struct nvk_addr_range addr_range =
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nvk_buffer_addr_range(buffer, pOffsets[i], size);
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assert(addr_range.range <= UINT32_MAX);
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struct nv_push *p = nvk_cmd_buffer_push(cmd, 5);
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P_MTHD(p, NV9097, SET_STREAM_OUT_BUFFER_ENABLE(idx));
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P_NV9097_SET_STREAM_OUT_BUFFER_ENABLE(p, idx, V_TRUE);
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P_NV9097_SET_STREAM_OUT_BUFFER_ADDRESS_A(p, idx, addr_range.addr >> 32);
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P_NV9097_SET_STREAM_OUT_BUFFER_ADDRESS_B(p, idx, addr_range.addr);
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P_NV9097_SET_STREAM_OUT_BUFFER_SIZE(p, idx, (uint32_t)addr_range.range);
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}
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// TODO: do we need to SET_STREAM_OUT_BUFFER_ENABLE V_FALSE ?
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}
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void
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nvk_mme_xfb_counter_load(struct mme_builder *b)
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{
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struct mme_value buffer = mme_load(b);
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struct mme_value counter;
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if (b->devinfo->cls_eng3d >= TURING_A) {
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struct mme_value64 counter_addr = mme_load_addr64(b);
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mme_tu104_read_fifoed(b, counter_addr, mme_imm(1));
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mme_free_reg(b, counter_addr.lo);
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mme_free_reg(b, counter_addr.hi);
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counter = mme_load(b);
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} else {
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counter = mme_load(b);
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}
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mme_mthd_arr(b, NV9097_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER(0), buffer);
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mme_emit(b, counter);
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mme_free_reg(b, counter);
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mme_free_reg(b, buffer);
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}
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VKAPI_ATTR void VKAPI_CALL
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nvk_CmdBeginTransformFeedbackEXT(VkCommandBuffer commandBuffer,
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uint32_t firstCounterBuffer,
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uint32_t counterBufferCount,
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const VkBuffer *pCounterBuffers,
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const VkDeviceSize *pCounterBufferOffsets)
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{
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VK_FROM_HANDLE(nvk_cmd_buffer, cmd, commandBuffer);
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const uint32_t max_buffers = 4;
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struct nv_push *p = nvk_cmd_buffer_push(cmd, 2 + 2 * max_buffers);
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P_IMMD(p, NV9097, SET_STREAM_OUTPUT, ENABLE_TRUE);
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for (uint32_t i = 0; i < max_buffers; ++i) {
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P_IMMD(p, NV9097, SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER(i), 0);
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}
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for (uint32_t i = 0; i < counterBufferCount; ++i) {
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if (pCounterBuffers[i] == VK_NULL_HANDLE)
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continue;
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VK_FROM_HANDLE(nvk_buffer, buffer, pCounterBuffers[i]);
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// index of counter buffer corresponts to index of transform buffer
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uint32_t cb_idx = firstCounterBuffer + i;
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uint64_t offset = pCounterBufferOffsets ? pCounterBufferOffsets[i] : 0;
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uint64_t cb_addr = nvk_buffer_address(buffer, offset);
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if (nvk_cmd_buffer_device(cmd)->pdev->info.cls_eng3d >= TURING_A) {
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struct nv_push *p = nvk_cmd_buffer_push(cmd, 6);
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P_IMMD(p, NVC597, SET_MME_DATA_FIFO_CONFIG, FIFO_SIZE_SIZE_4KB);
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P_1INC(p, NV9097, CALL_MME_MACRO(NVK_MME_XFB_COUNTER_LOAD));
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P_INLINE_DATA(p, cb_idx);
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P_INLINE_DATA(p, cb_addr >> 32);
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P_INLINE_DATA(p, cb_addr);
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} else {
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struct nv_push *p = nvk_cmd_buffer_push(cmd, 4);
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/* Stall the command streamer */
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__push_immd(p, SUBC_NV9097, NV906F_SET_REFERENCE, 0);
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P_1INC(p, NV9097, CALL_MME_MACRO(NVK_MME_XFB_COUNTER_LOAD));
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P_INLINE_DATA(p, cb_idx);
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nv_push_update_count(p, 1);
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nvk_cmd_buffer_push_indirect_buffer(cmd, buffer, offset, 4);
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}
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}
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}
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VKAPI_ATTR void VKAPI_CALL
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nvk_CmdEndTransformFeedbackEXT(VkCommandBuffer commandBuffer,
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uint32_t firstCounterBuffer,
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uint32_t counterBufferCount,
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const VkBuffer *pCounterBuffers,
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const VkDeviceSize *pCounterBufferOffsets)
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{
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VK_FROM_HANDLE(nvk_cmd_buffer, cmd, commandBuffer);
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for (uint32_t i = 0; i < counterBufferCount; ++i) {
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if (pCounterBuffers[i] == VK_NULL_HANDLE)
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continue;
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VK_FROM_HANDLE(nvk_buffer, buffer, pCounterBuffers[i]);
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uint64_t offset = pCounterBufferOffsets ? pCounterBufferOffsets[i] : 0;
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uint64_t cb_addr = nvk_buffer_address(buffer, offset);
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struct nv_push *p = nvk_cmd_buffer_push(cmd, 5);
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P_MTHD(p, NV9097, SET_REPORT_SEMAPHORE_A);
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P_NV9097_SET_REPORT_SEMAPHORE_A(p, cb_addr >> 32);
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P_NV9097_SET_REPORT_SEMAPHORE_B(p, cb_addr);
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P_NV9097_SET_REPORT_SEMAPHORE_C(p, 0);
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P_NV9097_SET_REPORT_SEMAPHORE_D(p, {
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.operation = OPERATION_REPORT_ONLY,
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.pipeline_location = PIPELINE_LOCATION_STREAMING_OUTPUT,
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.report = REPORT_STREAMING_BYTE_COUNT,
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.structure_size = STRUCTURE_SIZE_ONE_WORD,
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});
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}
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struct nv_push *p = nvk_cmd_buffer_push(cmd, counterBufferCount ? 4 : 2);
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P_IMMD(p, NV9097, SET_STREAM_OUTPUT, ENABLE_FALSE);
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// TODO: this probably needs to move to CmdPipelineBarrier
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if (counterBufferCount > 0) {
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P_MTHD(p, NVA0C0, INVALIDATE_SHADER_CACHES_NO_WFI);
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P_NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI(p, {
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.constant = CONSTANT_TRUE
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});
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}
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}
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@ -2576,6 +2576,152 @@ nvk_CmdDrawIndirectByteCountEXT(VkCommandBuffer commandBuffer,
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}
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}
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VKAPI_ATTR void VKAPI_CALL
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nvk_CmdBindTransformFeedbackBuffersEXT(VkCommandBuffer commandBuffer,
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uint32_t firstBinding,
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uint32_t bindingCount,
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const VkBuffer *pBuffers,
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const VkDeviceSize *pOffsets,
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const VkDeviceSize *pSizes)
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{
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VK_FROM_HANDLE(nvk_cmd_buffer, cmd, commandBuffer);
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for (uint32_t i = 0; i < bindingCount; i++) {
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VK_FROM_HANDLE(nvk_buffer, buffer, pBuffers[i]);
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uint32_t idx = firstBinding + i;
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uint64_t size = pSizes ? pSizes[i] : VK_WHOLE_SIZE;
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struct nvk_addr_range addr_range =
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nvk_buffer_addr_range(buffer, pOffsets[i], size);
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assert(addr_range.range <= UINT32_MAX);
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struct nv_push *p = nvk_cmd_buffer_push(cmd, 5);
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P_MTHD(p, NV9097, SET_STREAM_OUT_BUFFER_ENABLE(idx));
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P_NV9097_SET_STREAM_OUT_BUFFER_ENABLE(p, idx, V_TRUE);
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P_NV9097_SET_STREAM_OUT_BUFFER_ADDRESS_A(p, idx, addr_range.addr >> 32);
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P_NV9097_SET_STREAM_OUT_BUFFER_ADDRESS_B(p, idx, addr_range.addr);
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P_NV9097_SET_STREAM_OUT_BUFFER_SIZE(p, idx, (uint32_t)addr_range.range);
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}
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// TODO: do we need to SET_STREAM_OUT_BUFFER_ENABLE V_FALSE ?
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}
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void
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nvk_mme_xfb_counter_load(struct mme_builder *b)
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{
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struct mme_value buffer = mme_load(b);
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struct mme_value counter;
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if (b->devinfo->cls_eng3d >= TURING_A) {
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struct mme_value64 counter_addr = mme_load_addr64(b);
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mme_tu104_read_fifoed(b, counter_addr, mme_imm(1));
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mme_free_reg(b, counter_addr.lo);
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mme_free_reg(b, counter_addr.hi);
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counter = mme_load(b);
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} else {
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counter = mme_load(b);
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}
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mme_mthd_arr(b, NV9097_SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER(0), buffer);
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mme_emit(b, counter);
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mme_free_reg(b, counter);
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mme_free_reg(b, buffer);
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}
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VKAPI_ATTR void VKAPI_CALL
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nvk_CmdBeginTransformFeedbackEXT(VkCommandBuffer commandBuffer,
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uint32_t firstCounterBuffer,
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uint32_t counterBufferCount,
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const VkBuffer *pCounterBuffers,
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const VkDeviceSize *pCounterBufferOffsets)
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{
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VK_FROM_HANDLE(nvk_cmd_buffer, cmd, commandBuffer);
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const uint32_t max_buffers = 4;
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struct nv_push *p = nvk_cmd_buffer_push(cmd, 2 + 2 * max_buffers);
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P_IMMD(p, NV9097, SET_STREAM_OUTPUT, ENABLE_TRUE);
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for (uint32_t i = 0; i < max_buffers; ++i) {
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P_IMMD(p, NV9097, SET_STREAM_OUT_BUFFER_LOAD_WRITE_POINTER(i), 0);
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}
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for (uint32_t i = 0; i < counterBufferCount; ++i) {
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if (pCounterBuffers[i] == VK_NULL_HANDLE)
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continue;
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VK_FROM_HANDLE(nvk_buffer, buffer, pCounterBuffers[i]);
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// index of counter buffer corresponts to index of transform buffer
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uint32_t cb_idx = firstCounterBuffer + i;
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uint64_t offset = pCounterBufferOffsets ? pCounterBufferOffsets[i] : 0;
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uint64_t cb_addr = nvk_buffer_address(buffer, offset);
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if (nvk_cmd_buffer_device(cmd)->pdev->info.cls_eng3d >= TURING_A) {
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struct nv_push *p = nvk_cmd_buffer_push(cmd, 6);
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P_IMMD(p, NVC597, SET_MME_DATA_FIFO_CONFIG, FIFO_SIZE_SIZE_4KB);
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P_1INC(p, NV9097, CALL_MME_MACRO(NVK_MME_XFB_COUNTER_LOAD));
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P_INLINE_DATA(p, cb_idx);
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P_INLINE_DATA(p, cb_addr >> 32);
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P_INLINE_DATA(p, cb_addr);
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} else {
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struct nv_push *p = nvk_cmd_buffer_push(cmd, 4);
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/* Stall the command streamer */
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__push_immd(p, SUBC_NV9097, NV906F_SET_REFERENCE, 0);
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P_1INC(p, NV9097, CALL_MME_MACRO(NVK_MME_XFB_COUNTER_LOAD));
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P_INLINE_DATA(p, cb_idx);
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nv_push_update_count(p, 1);
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nvk_cmd_buffer_push_indirect_buffer(cmd, buffer, offset, 4);
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}
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}
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}
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#include "nvk_cla0c0.h"
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VKAPI_ATTR void VKAPI_CALL
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nvk_CmdEndTransformFeedbackEXT(VkCommandBuffer commandBuffer,
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uint32_t firstCounterBuffer,
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uint32_t counterBufferCount,
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const VkBuffer *pCounterBuffers,
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const VkDeviceSize *pCounterBufferOffsets)
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{
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VK_FROM_HANDLE(nvk_cmd_buffer, cmd, commandBuffer);
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for (uint32_t i = 0; i < counterBufferCount; ++i) {
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if (pCounterBuffers[i] == VK_NULL_HANDLE)
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continue;
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VK_FROM_HANDLE(nvk_buffer, buffer, pCounterBuffers[i]);
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uint64_t offset = pCounterBufferOffsets ? pCounterBufferOffsets[i] : 0;
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uint64_t cb_addr = nvk_buffer_address(buffer, offset);
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struct nv_push *p = nvk_cmd_buffer_push(cmd, 5);
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P_MTHD(p, NV9097, SET_REPORT_SEMAPHORE_A);
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P_NV9097_SET_REPORT_SEMAPHORE_A(p, cb_addr >> 32);
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P_NV9097_SET_REPORT_SEMAPHORE_B(p, cb_addr);
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P_NV9097_SET_REPORT_SEMAPHORE_C(p, 0);
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P_NV9097_SET_REPORT_SEMAPHORE_D(p, {
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.operation = OPERATION_REPORT_ONLY,
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.pipeline_location = PIPELINE_LOCATION_STREAMING_OUTPUT,
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.report = REPORT_STREAMING_BYTE_COUNT,
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.structure_size = STRUCTURE_SIZE_ONE_WORD,
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});
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}
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struct nv_push *p = nvk_cmd_buffer_push(cmd, counterBufferCount ? 4 : 2);
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P_IMMD(p, NV9097, SET_STREAM_OUTPUT, ENABLE_FALSE);
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// TODO: this probably needs to move to CmdPipelineBarrier
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if (counterBufferCount > 0) {
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P_MTHD(p, NVA0C0, INVALIDATE_SHADER_CACHES_NO_WFI);
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P_NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI(p, {
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.constant = CONSTANT_TRUE
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});
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}
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}
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VKAPI_ATTR void VKAPI_CALL
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nvk_CmdBeginConditionalRenderingEXT(VkCommandBuffer commandBuffer,
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const VkConditionalRenderingBeginInfoEXT *pConditionalRenderingBegin)
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