fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-05 18:18:06 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

freedreno/a6xx: Emit a WFI after event writes flushing CCU.

Browse source 
Following on from !12475, do the same CCU workaround for freedreno as
turnip is doing, so that we flush CCU correctly for when color/depth is
next read under a different cache domain from where it was written.

Fixes instability (particularly if the GPU is clocked up) on
dEQP-GLES3.functional.fbo.blit.depth_stencil.depth32f_stencil8* in bypass
mode on a630.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11481>
This commit is contained in:
Emma Anholt 2021-08-18 10:08:15 -07:00 • committed by Marge Bot
parent 69e96cfc0d
commit edfff331b3
5 changed files with 10 additions and 7 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

5
src/freedreno/ci/deqp-freedreno-a630-flakes.txt
View file

@ -91,11 +91,6 @@ dEQP-GLES31.functional.layout_binding.ssbo.fragment_binding_array
dEQP-GLES3.functional.fbo.blit.conversion.rg8i_to_r16i
dEQP-GLES3.functional.fbo.blit.conversion.rg8_to_r16f
# Started appearing after disabling cpufreq, devfreq and disabling runtime PM
dEQP-GLES3.functional.fbo.blit.depth_stencil.depth32f_stencil8_basic
dEQP-GLES3.functional.fbo.blit.depth_stencil.depth32f_stencil8_scale
dEQP-GLES3.functional.fbo.blit.depth_stencil.depth32f_stencil8_stencil_only
# Could trip hangcheck timeout
dEQP-VK.api.command_buffers.record_many_draws_primary_2
dEQP-VK.api.command_buffers.record_many_draws_secondary_2

3
src/gallium/drivers/freedreno/a6xx/fd6_blitter.c
View file

@ -524,6 +524,7 @@ fd6_clear_ubwc(struct fd_batch *batch, struct fd_resource *rsc) assert_dt
fd6_event_write(batch, ring, PC_CCU_FLUSH_COLOR_TS, true);
fd6_event_write(batch, ring, PC_CCU_FLUSH_DEPTH_TS, true);
fd6_event_write(batch, ring, CACHE_FLUSH_TS, true);
fd_wfi(batch, ring);
fd6_cache_inv(batch, ring);
}
@ -893,6 +894,7 @@ fd6_resolve_tile(struct fd_batch *batch, struct fd_ringbuffer *ring,
* results in sysmem, so we need to flush manually here.
*/
fd6_event_write(batch, ring, PC_CCU_FLUSH_COLOR_TS, true);
fd_wfi(batch, ring);
}
static bool
@ -956,6 +958,7 @@ handle_rgba_blit(struct fd_context *ctx,
fd6_event_write(batch, batch->draw, PC_CCU_FLUSH_COLOR_TS, true);
fd6_event_write(batch, batch->draw, PC_CCU_FLUSH_DEPTH_TS, true);
fd6_event_write(batch, batch->draw, CACHE_FLUSH_TS, true);
fd_wfi(batch, batch->draw);
fd6_cache_inv(batch, batch->draw);
fd_batch_unlock_submit(batch);

4
src/gallium/drivers/freedreno/a6xx/fd6_draw.c
View file

@ -373,7 +373,7 @@ fd6_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info,
}
static void
fd6_clear_lrz(struct fd_batch *batch, struct fd_resource *zsbuf, double depth)
fd6_clear_lrz(struct fd_batch *batch, struct fd_resource *zsbuf, double depth) assert_dt
{
struct fd_ringbuffer *ring;
struct fd_screen *screen = batch->ctx->screen;
@ -432,6 +432,7 @@ fd6_clear_lrz(struct fd_batch *batch, struct fd_resource *zsbuf, double depth)
fd6_event_write(batch, ring, PC_CCU_FLUSH_COLOR_TS, true);
fd6_event_write(batch, ring, PC_CCU_INVALIDATE_COLOR, false);
fd_wfi(batch, ring);
OUT_PKT4(ring, REG_A6XX_RB_2D_SRC_SOLID_C0, 4);
OUT_RING(ring, fui(depth));
@ -477,6 +478,7 @@ fd6_clear_lrz(struct fd_batch *batch, struct fd_resource *zsbuf, double depth)
fd6_event_write(batch, ring, PC_CCU_FLUSH_COLOR_TS, true);
fd6_event_write(batch, ring, PC_CCU_FLUSH_DEPTH_TS, true);
fd6_event_write(batch, ring, CACHE_FLUSH_TS, true);
fd_wfi(batch, ring);
fd6_cache_inv(batch, ring);
}

1
src/gallium/drivers/freedreno/a6xx/fd6_emit.c
View file

@ -1413,6 +1413,7 @@ fd6_framebuffer_barrier(struct fd_context *ctx) assert_dt
fd6_event_write(batch, ring, PC_CCU_FLUSH_DEPTH_TS, true);
seqno = fd6_event_write(batch, ring, CACHE_FLUSH_TS, true);
fd_wfi(batch, ring);
fd6_event_write(batch, ring, 0x31, false);

4
src/gallium/drivers/freedreno/a6xx/fd6_gmem.c
View file

@ -1512,6 +1512,7 @@ emit_sysmem_clears(struct fd_batch *batch, struct fd_ringbuffer *ring) assert_dt
}
fd6_event_write(batch, ring, PC_CCU_FLUSH_COLOR_TS, true);
fd_wfi(batch, ring);
trace_end_clear_restore(&batch->trace);
}
@ -1609,7 +1610,7 @@ fd6_emit_sysmem_prep(struct fd_batch *batch) assert_dt
}
static void
fd6_emit_sysmem_fini(struct fd_batch *batch)
fd6_emit_sysmem_fini(struct fd_batch *batch) assert_dt
{
struct fd_ringbuffer *ring = batch->gmem;
@ -1625,6 +1626,7 @@ fd6_emit_sysmem_fini(struct fd_batch *batch)
fd6_event_write(batch, ring, PC_CCU_FLUSH_COLOR_TS, true);
fd6_event_write(batch, ring, PC_CCU_FLUSH_DEPTH_TS, true);
fd_wfi(batch, ring);
}
void