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nak: Fix the encoding of OpShfl

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We weren't handling Zero.  Also, we need to mask immediates or else the
encoder blows up.  The hardware automatically masks them when they come
in as sources but when we get immediates, they're not guaranteed to fit
in the bitfield.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24998>
This commit is contained in:
Faith Ekstrand 2023-10-24 15:00:08 -05:00 • committed by Marge Bot
parent 5dd7a76c8b
commit edf015eb7f
1 changed files with 7 additions and 7 deletions
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14
src/nouveau/compiler/nak_encode_sm75.rs
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@ -883,8 +883,8 @@ impl SM75Instr {
assert!(op.c.src_mod.is_none());
match &op.lane.src_ref {
SrcRef::Reg(_) => match &op.c.src_ref {
SrcRef::Reg(_) => {
SrcRef::Zero | SrcRef::Reg(_) => match &op.c.src_ref {
SrcRef::Zero | SrcRef::Reg(_) => {
self.set_opcode(0x389);
self.set_reg_src(32..40, op.lane);
self.set_reg_src(64..72, op.c);
@ -892,20 +892,20 @@ impl SM75Instr {
SrcRef::Imm32(imm_c) => {
self.set_opcode(0x589);
self.set_reg_src(32..40, op.lane);
self.set_field(40..53, *imm_c);
self.set_field(40..53, *imm_c & 0x1f1f);
}
_ => panic!("Invalid instruction form"),
},
SrcRef::Imm32(imm_lane) => match &op.c.src_ref {
SrcRef::Reg(_) => {
SrcRef::Zero | SrcRef::Reg(_) => {
self.set_opcode(0x989);
self.set_field(53..58, *imm_lane);
self.set_field(53..58, *imm_lane & 0x1f);
self.set_reg_src(64..72, op.c);
}
SrcRef::Imm32(imm_c) => {
self.set_opcode(0xf89);
self.set_field(40..53, *imm_c);
self.set_field(53..58, *imm_lane);
self.set_field(40..53, *imm_c & 0x1f1f);
self.set_field(53..58, *imm_lane & 0x1f);
}
_ => panic!("Invalid instruction form"),
},