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i965/blorp: Use 8k chunk size for urb allocation

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Previously, we hardcoded "VS URB Starting Address" to 2 (in 8kB chunks),
which meant VS URB data would start at an offset of 16kB.

However, on Haswell GT3 and Gen8+, we allocate the first 32kB for the
push constant region.  This means that the PS push constant and VS URB
data regions overlap, which can lead to corruption.

v2 (Ken): Better description of the change, and do not change vs_size
          from 2 to 1.

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Topi Pohjolainen 2016-04-15 10:12:20 +03:00
parent e04b3cdf33
commit ede09e672a
1 changed files with 14 additions and 5 deletions
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19
src/mesa/drivers/dri/i965/gen7_blorp.cpp
View file

@ -47,8 +47,17 @@
static void
gen7_blorp_emit_urb_config(struct brw_context *brw)
{
/* URB allocations must be done in 8k chunks. */
const unsigned chunk_size_bytes = 8192;
const unsigned urb_size =
(brw->gen >= 8 || (brw->is_haswell && brw->gt == 3)) ? 32 : 16;
const unsigned push_constant_bytes = 1024 * urb_size;
const unsigned push_constant_chunks =
push_constant_bytes / chunk_size_bytes;
const unsigned vs_size = 2;
const unsigned vs_start = push_constant_chunks;
const unsigned vs_chunks =
DIV_ROUND_UP(brw->urb.min_vs_entries * vs_size * 64, chunk_size_bytes);
gen7_emit_push_constant_state(brw,
urb_size / 2 /* vs_size */,
@ -59,17 +68,17 @@ gen7_blorp_emit_urb_config(struct brw_context *brw)
gen7_emit_urb_state(brw,
brw->urb.min_vs_entries /* num_vs_entries */,
2 /* vs_size */,
2 /* vs_start */,
vs_size,
vs_start,
0 /* num_hs_entries */,
1 /* hs_size */,
2 /* hs_start */,
vs_start + vs_chunks /* hs_start */,
0 /* num_ds_entries */,
1 /* ds_size */,
2 /* ds_start */,
vs_start + vs_chunks /* ds_start */,
0 /* num_gs_entries */,
1 /* gs_size */,
2 /* gs_start */);
vs_start + vs_chunks /* gs_start */);
}