From edce6f410fc7ae30e5c577285d04aa97202eb94b Mon Sep 17 00:00:00 2001 From: Job Noorman Date: Thu, 26 Jun 2025 11:35:54 +0200 Subject: [PATCH] ir3: support half regs for read_{first,cond,getlast} The emitted mov had a hard coded dst type of u32. This was fine because we needed this to work around a HW bug with shared half movs. However, since this bug was fixed in a7xx, we need to support half movs as well. Signed-off-by: Job Noorman Part-of: --- src/freedreno/ir3/ir3_lower_subgroups.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/freedreno/ir3/ir3_lower_subgroups.c b/src/freedreno/ir3/ir3_lower_subgroups.c index 310bcc857ff..0aa7561ac1b 100644 --- a/src/freedreno/ir3/ir3_lower_subgroups.c +++ b/src/freedreno/ir3/ir3_lower_subgroups.c @@ -273,7 +273,8 @@ lower_instr(struct ir3 *ir, struct ir3_block **block, struct ir3_instruction *in */ assert(instr->dsts[0]->flags & IR3_REG_SHARED); instr->opc = OPC_MOV; - instr->cat1.dst_type = TYPE_U32; + instr->cat1.dst_type = + (instr->dsts[0]->flags & IR3_REG_HALF) ? TYPE_U16 : TYPE_U32; instr->cat1.src_type = (instr->srcs[0]->flags & IR3_REG_HALF) ? TYPE_U16 : TYPE_U32; return false; @@ -487,7 +488,8 @@ lower_instr(struct ir3 *ir, struct ir3_block **block, struct ir3_instruction *in struct ir3_register *new_src = ir3_src_create(mov, 0, 0); unsigned idx = instr->opc == OPC_READ_COND_MACRO ? 1 : 0; *new_src = *instr->srcs[idx]; - mov->cat1.dst_type = TYPE_U32; + mov->cat1.dst_type = + (instr->dsts[0]->flags & IR3_REG_HALF) ? TYPE_U16 : TYPE_U32; mov->cat1.src_type = (new_src->flags & IR3_REG_HALF) ? TYPE_U16 : TYPE_U32; mov->flags |= IR3_INSTR_NEEDS_HELPERS;