fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2025-12-24 04:30:10 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

pan/mdg: Reorder some code in mir_spill_register

Browse source 
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11212>
This commit is contained in:
Icecream95 2021-06-07 19:25:42 +12:00 • committed by Marge Bot
parent 1490e7e622
commit ed9a9a09f2
1 changed files with 17 additions and 16 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

31
src/panfrost/midgard/midgard_ra.c
View file

@ -862,6 +862,13 @@ mir_spill_register(
/* Allocate TLS slot (maybe) */ /* Allocate TLS slot (maybe) */
unsigned spill_slot = !is_special ? (*spill_count)++ : 0; unsigned spill_slot = !is_special ? (*spill_count)++ : 0;
/* For special reads, figure out how many bytes we need */
unsigned read_bytemask = 0;
mir_foreach_instr_global_safe(ctx, ins) {
read_bytemask |= mir_bytemask_of_read_components(ins, spill_node);
}
/* For TLS, replace all stores to the spilled node. For /* For TLS, replace all stores to the spilled node. For
* special reads, just keep as-is; the class will be demoted * special reads, just keep as-is; the class will be demoted
* implicitly. For special writes, spill to a work register */ * implicitly. For special writes, spill to a work register */
@ -875,8 +882,6 @@ mir_spill_register(
mir_foreach_instr_in_block_safe(block, ins) { mir_foreach_instr_in_block_safe(block, ins) {
if (ins->dest != spill_node) continue; if (ins->dest != spill_node) continue;
midgard_instruction st;
/* Note: it's important to match the mask of the spill /* Note: it's important to match the mask of the spill
* with the mask of the instruction whose destination * with the mask of the instruction whose destination
* we're spilling, or otherwise we'll read invalid * we're spilling, or otherwise we'll read invalid
@ -884,20 +889,23 @@ mir_spill_register(
*/ */
if (is_special_w) { if (is_special_w) {
st = v_mov(spill_node, spill_slot); midgard_instruction st = v_mov(spill_node, spill_slot);
st.no_spill |= (1 << spill_class); st.no_spill |= (1 << spill_class);
st.mask = ins->mask; st.mask = ins->mask;
st.dest_type = st.src_types[1] = ins->dest_type; st.dest_type = st.src_types[1] = ins->dest_type;
} else {
ins->dest = spill_index++;
ins->no_spill |= (1 << spill_class);
st = v_load_store_scratch(ins->dest, spill_slot, true, ins->mask);
}
/* Hint: don't rewrite this node */ /* Hint: don't rewrite this node */
st.hint = true; st.hint = true;
mir_insert_instruction_after_scheduled(ctx, block, ins, st); mir_insert_instruction_after_scheduled(ctx, block, ins, st);
} else {
ins->dest = spill_index++;
ins->no_spill |= (1 << spill_class);
midgard_instruction st =
v_load_store_scratch(ins->dest, spill_slot, true, ins->mask);
mir_insert_instruction_after_scheduled(ctx, block, ins, st);
}
if (!is_special) if (!is_special)
ctx->spills++; ctx->spills++;
@ -905,13 +913,6 @@ mir_spill_register(
} }
} }
/* For special reads, figure out how many bytes we need */
unsigned read_bytemask = 0;
mir_foreach_instr_global_safe(ctx, ins) {
read_bytemask |= mir_bytemask_of_read_components(ins, spill_node);
}
/* Insert a load from TLS before the first consecutive /* Insert a load from TLS before the first consecutive
* use of the node, rewriting to use spilled indices to * use of the node, rewriting to use spilled indices to
* break up the live range. Or, for special, insert a * break up the live range. Or, for special, insert a