diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c
index e0e540e12e3..206cb4f63c5 100644
--- a/src/gallium/drivers/iris/iris_state.c
+++ b/src/gallium/drivers/iris/iris_state.c
@@ -6768,6 +6768,7 @@ iris_upload_dirty_render_state(struct iris_context *ice,
             tbimr.VerticalTileCount = DIV_ROUND_UP(cso_fb->height, tile_height);
             tbimr.HorizontalTileCount = DIV_ROUND_UP(cso_fb->width, tile_width);
             tbimr.TBIMRBatchSize = util_logbase2(batch_size) - 5;
+            tbimr.TileBoxCheck = true;
          }
       }
    }
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index 3e5dfabecd4..3bb8c5918f2 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -1439,6 +1439,7 @@ struct anv_gfx_dynamic_state {
       unsigned VerticalTileCount;
       unsigned HorizontalTileCount;
       unsigned TBIMRBatchSize;
+      unsigned TileBoxCheck;
    } tbimr;
    bool use_tbimr;
 
diff --git a/src/intel/vulkan/genX_gfx_state.c b/src/intel/vulkan/genX_gfx_state.c
index c3d791268cd..d2cd30dfbe0 100644
--- a/src/intel/vulkan/genX_gfx_state.c
+++ b/src/intel/vulkan/genX_gfx_state.c
@@ -1280,6 +1280,7 @@ genX(cmd_buffer_flush_gfx_runtime_state)(struct anv_cmd_buffer *cmd_buffer)
              DIV_ROUND_UP(fb_width, tile_width));
          SET(TBIMR_TILE_PASS_INFO, tbimr.TBIMRBatchSize,
              util_logbase2(batch_size) - 5);
+         SET(TBIMR_TILE_PASS_INFO, tbimr.TileBoxCheck, true);
          SET(TBIMR_TILE_PASS_INFO, use_tbimr, true);
       } else {
          hw_state->use_tbimr = false;
@@ -1891,6 +1892,7 @@ genX(cmd_buffer_flush_gfx_hw_state)(struct anv_cmd_buffer *cmd_buffer)
          SET(tbimr, tbimr, VerticalTileCount);
          SET(tbimr, tbimr, HorizontalTileCount);
          SET(tbimr, tbimr, TBIMRBatchSize);
+         SET(tbimr, tbimr, TileBoxCheck);
       }
    }
 #endif