fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-01-03 05:00:09 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

gallium: remove enum numbers from shader cap queries

Browse source 
The enum numbers were just cruft.

Reviewed-by: Michel Dänzer <michel@daenzer.net>
This commit is contained in:
Brian Paul 2014-05-03 07:27:48 -06:00
parent f7bf37cb13
commit ed8bfaba52
1 changed files with 32 additions and 32 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

64
src/gallium/include/pipe/p_defines.h
View file

@ -578,44 +578,44 @@ enum pipe_endian {
*/
enum pipe_capf
{
PIPE_CAPF_MAX_LINE_WIDTH = 15,
PIPE_CAPF_MAX_LINE_WIDTH_AA = 16,
PIPE_CAPF_MAX_POINT_WIDTH = 17,
PIPE_CAPF_MAX_POINT_WIDTH_AA = 18,
PIPE_CAPF_MAX_TEXTURE_ANISOTROPY = 19,
PIPE_CAPF_MAX_TEXTURE_LOD_BIAS = 20,
PIPE_CAPF_GUARD_BAND_LEFT = 21,
PIPE_CAPF_GUARD_BAND_TOP = 22,
PIPE_CAPF_GUARD_BAND_RIGHT = 23,
PIPE_CAPF_GUARD_BAND_BOTTOM = 24
PIPE_CAPF_MAX_LINE_WIDTH,
PIPE_CAPF_MAX_LINE_WIDTH_AA,
PIPE_CAPF_MAX_POINT_WIDTH,
PIPE_CAPF_MAX_POINT_WIDTH_AA,
PIPE_CAPF_MAX_TEXTURE_ANISOTROPY,
PIPE_CAPF_MAX_TEXTURE_LOD_BIAS,
PIPE_CAPF_GUARD_BAND_LEFT,
PIPE_CAPF_GUARD_BAND_TOP,
PIPE_CAPF_GUARD_BAND_RIGHT,
PIPE_CAPF_GUARD_BAND_BOTTOM
};
/* Shader caps not specific to any single stage */
enum pipe_shader_cap
{
PIPE_SHADER_CAP_MAX_INSTRUCTIONS = 0, /* if 0, it means the stage is unsupported */
PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS = 1,
PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS = 2,
PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS = 3,
PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH = 4,
PIPE_SHADER_CAP_MAX_INPUTS = 5,
PIPE_SHADER_CAP_MAX_CONSTS = 6,
PIPE_SHADER_CAP_MAX_CONST_BUFFERS = 7,
PIPE_SHADER_CAP_MAX_TEMPS = 8,
PIPE_SHADER_CAP_MAX_ADDRS = 9,
PIPE_SHADER_CAP_MAX_PREDS = 10,
PIPE_SHADER_CAP_MAX_INSTRUCTIONS, /* if 0, it means the stage is unsupported */
PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS,
PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS,
PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS,
PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH,
PIPE_SHADER_CAP_MAX_INPUTS,
PIPE_SHADER_CAP_MAX_CONSTS,
PIPE_SHADER_CAP_MAX_CONST_BUFFERS,
PIPE_SHADER_CAP_MAX_TEMPS,
PIPE_SHADER_CAP_MAX_ADDRS,
PIPE_SHADER_CAP_MAX_PREDS,
/* boolean caps */
PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED = 11,
PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR = 12,
PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR = 13,
PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR = 14,
PIPE_SHADER_CAP_INDIRECT_CONST_ADDR = 15,
PIPE_SHADER_CAP_SUBROUTINES = 16, /* BGNSUB, ENDSUB, CAL, RET */
PIPE_SHADER_CAP_INTEGERS = 17,
PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS = 18,
PIPE_SHADER_CAP_PREFERRED_IR = 19,
PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED = 20,
PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS = 21
PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED,
PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR,
PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR,
PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR,
PIPE_SHADER_CAP_INDIRECT_CONST_ADDR,
PIPE_SHADER_CAP_SUBROUTINES, /* BGNSUB, ENDSUB, CAL, RET */
PIPE_SHADER_CAP_INTEGERS,
PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS,
PIPE_SHADER_CAP_PREFERRED_IR,
PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED,
PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
};
/**