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radeonsi: implement GL_INTEL_blackhole_render
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7031>
This commit is contained in:
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bad7b38aa1
commit
ed3c5fe469
9 changed files with 25 additions and 2 deletions
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@ -1,4 +1,5 @@
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GL 4.5 on llvmpipe
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GL 4.5 on llvmpipe
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GL_INTEL_blackhole_render on radeonsi
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GL_NV_copy_depth_to_color for NIR
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GL_NV_copy_depth_to_color for NIR
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GL_NV_half_float
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GL_NV_half_float
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GL_NV_shader_atomic_int64 on radeonsi
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GL_NV_shader_atomic_int64 on radeonsi
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@ -28,6 +28,9 @@
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/* The public winsys interface header for the radeon driver. */
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/* The public winsys interface header for the radeon driver. */
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/* Skip command submission. Same as RADEON_NOOP=1. */
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#define RADEON_FLUSH_NOOP (1u << 30)
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/* Whether the next IB can start immediately and not wait for draws and
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/* Whether the next IB can start immediately and not wait for draws and
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* dispatches from the current IB to finish. */
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* dispatches from the current IB to finish. */
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#define RADEON_FLUSH_START_NEXT_GFX_IB_NOW (1u << 31)
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#define RADEON_FLUSH_START_NEXT_GFX_IB_NOW (1u << 31)
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@ -300,6 +300,9 @@ void si_flush_dma_cs(struct si_context *ctx, unsigned flags, struct pipe_fence_h
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if (check_vm)
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if (check_vm)
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si_save_cs(ctx->ws, cs, &saved, true);
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si_save_cs(ctx->ws, cs, &saved, true);
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if (ctx->is_noop)
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flags |= RADEON_FLUSH_NOOP;
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ctx->ws->cs_flush(cs, flags, &ctx->last_sdma_fence);
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ctx->ws->cs_flush(cs, flags, &ctx->last_sdma_fence);
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if (fence)
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if (fence)
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ctx->ws->fence_reference(fence, ctx->last_sdma_fence);
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ctx->ws->fence_reference(fence, ctx->last_sdma_fence);
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@ -162,6 +162,7 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
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case PIPE_CAP_MAP_UNSYNCHRONIZED_THREAD_SAFE:
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case PIPE_CAP_MAP_UNSYNCHRONIZED_THREAD_SAFE:
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case PIPE_CAP_NO_CLIP_ON_COPY_TEX:
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case PIPE_CAP_NO_CLIP_ON_COPY_TEX:
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case PIPE_CAP_SHADER_ATOMIC_INT64:
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case PIPE_CAP_SHADER_ATOMIC_INT64:
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case PIPE_CAP_FRONTEND_NOOP:
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return 1;
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return 1;
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case PIPE_CAP_GLSL_ZERO_INIT:
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case PIPE_CAP_GLSL_ZERO_INIT:
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@ -227,6 +227,9 @@ void si_flush_gfx_cs(struct si_context *ctx, unsigned flags, struct pipe_fence_h
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}
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}
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}
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}
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if (ctx->is_noop)
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flags |= RADEON_FLUSH_NOOP;
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/* Flush the CS. */
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/* Flush the CS. */
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ws->cs_flush(cs, flags, &ctx->last_gfx_fence);
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ws->cs_flush(cs, flags, &ctx->last_gfx_fence);
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if (fence)
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if (fence)
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@ -423,6 +423,14 @@ static void si_set_context_param(struct pipe_context *ctx, enum pipe_context_par
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}
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}
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}
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}
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static void si_set_frontend_noop(struct pipe_context *ctx, bool enable)
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{
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struct si_context *sctx = (struct si_context *)ctx;
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ctx->flush(ctx, NULL, PIPE_FLUSH_ASYNC);
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sctx->is_noop = enable;
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}
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static struct pipe_context *si_create_context(struct pipe_screen *screen, unsigned flags)
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static struct pipe_context *si_create_context(struct pipe_screen *screen, unsigned flags)
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{
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{
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struct si_screen *sscreen = (struct si_screen *)screen;
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struct si_screen *sscreen = (struct si_screen *)screen;
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@ -556,6 +564,7 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, unsign
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sctx->b.set_context_param = si_set_context_param;
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sctx->b.set_context_param = si_set_context_param;
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sctx->b.get_device_reset_status = si_get_reset_status;
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sctx->b.get_device_reset_status = si_get_reset_status;
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sctx->b.set_device_reset_callback = si_set_device_reset_callback;
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sctx->b.set_device_reset_callback = si_set_device_reset_callback;
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sctx->b.set_frontend_noop = si_set_frontend_noop;
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si_init_all_descriptors(sctx);
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si_init_all_descriptors(sctx);
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si_init_buffer_functions(sctx);
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si_init_buffer_functions(sctx);
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@ -954,6 +954,7 @@ struct si_context {
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unsigned wait_mem_number;
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unsigned wait_mem_number;
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uint16_t prefetch_L2_mask;
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uint16_t prefetch_L2_mask;
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bool is_noop;
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bool has_graphics;
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bool has_graphics;
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bool gfx_flush_in_progress : 1;
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bool gfx_flush_in_progress : 1;
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bool gfx_last_ib_is_busy : 1;
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bool gfx_last_ib_is_busy : 1;
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@ -1796,7 +1796,8 @@ static int amdgpu_cs_flush(struct radeon_cmdbuf *rcs,
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/* If the CS is not empty or overflowed.... */
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/* If the CS is not empty or overflowed.... */
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if (likely(radeon_emitted(&cs->main.base, 0) &&
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if (likely(radeon_emitted(&cs->main.base, 0) &&
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cs->main.base.current.cdw <= cs->main.base.current.max_dw &&
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cs->main.base.current.cdw <= cs->main.base.current.max_dw &&
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!debug_get_option_noop())) {
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!debug_get_option_noop() &&
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!(flags & RADEON_FLUSH_NOOP))) {
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struct amdgpu_cs_context *cur = cs->csc;
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struct amdgpu_cs_context *cur = cs->csc;
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/* Set IB sizes. */
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/* Set IB sizes. */
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@ -638,7 +638,8 @@ static int radeon_drm_cs_flush(struct radeon_cmdbuf *rcs,
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cs->cst = tmp;
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cs->cst = tmp;
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/* If the CS is not empty or overflowed, emit it in a separate thread. */
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/* If the CS is not empty or overflowed, emit it in a separate thread. */
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if (cs->base.current.cdw && cs->base.current.cdw <= cs->base.current.max_dw && !debug_get_option_noop()) {
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if (cs->base.current.cdw && cs->base.current.cdw <= cs->base.current.max_dw &&
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!debug_get_option_noop() && !(flags & RADEON_FLUSH_NOOP)) {
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unsigned i, num_relocs;
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unsigned i, num_relocs;
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num_relocs = cs->cst->num_relocs;
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num_relocs = cs->cst->num_relocs;
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