diff --git a/src/gallium/drivers/etnaviv/etnaviv_emit.c b/src/gallium/drivers/etnaviv/etnaviv_emit.c
index 48167a7fe9b..0bc635d6f10 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_emit.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_emit.c
@@ -673,7 +673,7 @@ etna_emit_state(struct etna_context *ctx)
 
       } else if (ctx->shader_state.VS_INST_ADDR.bo || ctx->shader_state.PS_INST_ADDR.bo) {
          /* ICACHE (pre-HALTI5) */
-         assert(screen->specs.has_icache && screen->specs.has_shader_range_registers);
+         assert(screen->specs.has_icache && screen->specs.has_unified_instmem);
          /* Set icache (VS) */
          etna_set_state(stream, VIVS_VS_RANGE, (ctx->shader_state.vs_inst_mem_size / 4 - 1) << 16);
          etna_set_state(stream, VIVS_VS_ICACHE_CONTROL,
@@ -697,7 +697,7 @@ etna_emit_state(struct etna_context *ctx)
                   VIVS_VS_ICACHE_CONTROL_FLUSH_PS |
                   VIVS_VS_ICACHE_CONTROL_FLUSH_VS);
          }
-         if (screen->specs.has_shader_range_registers) {
+         if (screen->specs.has_unified_instmem) {
             etna_set_state(stream, VIVS_VS_RANGE, (ctx->shader_state.vs_inst_mem_size / 4 - 1) << 16);
             etna_set_state(stream, VIVS_PS_RANGE, ((ctx->shader_state.ps_inst_mem_size / 4 - 1 + 0x100) << 16) |
                                         0x100);
diff --git a/src/gallium/drivers/etnaviv/etnaviv_internal.h b/src/gallium/drivers/etnaviv/etnaviv_internal.h
index b45daba4e24..3739bca61f1 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_internal.h
+++ b/src/gallium/drivers/etnaviv/etnaviv_internal.h
@@ -70,7 +70,7 @@ struct etna_specs {
    /* needs z=(z+w)/2, for older GCxxx */
    unsigned vs_need_z_div : 1;
    /* can use VS_RANGE, PS_RANGE registers*/
-   unsigned has_shader_range_registers : 1;
+   unsigned has_unified_instmem : 1;
    /* has the new sin/cos/log functions */
    unsigned has_new_transcendentals : 1;
    /* has no limit on the number of constant sources per instruction */
diff --git a/src/gallium/drivers/etnaviv/etnaviv_screen.c b/src/gallium/drivers/etnaviv/etnaviv_screen.c
index 5f0c33a9a21..6068f1ca3e9 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_screen.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_screen.c
@@ -850,8 +850,7 @@ etna_get_specs(struct etna_screen *screen)
 
    screen->specs.vs_need_z_div =
       screen->info->model < 0x1000 && screen->info->model != 0x880;
-   screen->specs.has_shader_range_registers =
-      screen->info->model >= 0x1000 || screen->info->model == 0x880;
+   screen->specs.has_unified_instmem = instruction_count > 256;
    screen->specs.has_new_transcendentals =
       VIV_FEATURE(screen, ETNA_FEATURE_HAS_FAST_TRANSCENDENTALS);
    screen->specs.has_no_oneconst_limit =
@@ -869,8 +868,8 @@ etna_get_specs(struct etna_screen *screen)
       screen->specs.max_instructions = 0; /* Do not program shaders manually */
       screen->specs.has_icache = true;
    } else if (VIV_FEATURE(screen, ETNA_FEATURE_INSTRUCTION_CACHE)) {
-      /* GC3000 - this core is capable of loading shaders from
-       * memory. It can also run shaders from registers as a fallback, but the
+      /* GC3000 - this core is capable of loading shaders from memory. It can
+       * also run shaders from unified instruction states as a fallback, but the
        * offsets are slightly different.
        */
       screen->specs.vs_offset = 0xC000;
@@ -882,7 +881,8 @@ etna_get_specs(struct etna_screen *screen)
       screen->specs.max_instructions = 256; /* maximum number instructions for non-icache use */
       screen->specs.has_icache = true;
    } else {
-      if (instruction_count > 256) { /* unified instruction memory? */
+      if (instruction_count > 256) {
+         /* unified instruction states */
          screen->specs.vs_offset = 0xC000;
          screen->specs.ps_offset = 0xD000; /* like vivante driver */
          screen->specs.max_instructions = 256;