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intel/nir: add reloc delta to load_reloc_const_intel intrinsic

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We'll use the delta for an upcoming internal printf mechanism, where
the PARAM_IDX will be the base printf reloc identifier and the BASE
will be the string id.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25814>
This commit is contained in:
Lionel Landwerlin 2023-09-08 00:05:13 +03:00 • committed by Marge Bot
parent dde91d18c2
commit ecbec25e84
5 changed files with 10 additions and 7 deletions
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2
src/compiler/nir/nir_intrinsics.py
View file

@ -2094,7 +2094,7 @@ system_value("simd_width_intel", 1)
# Load a relocatable 32-bit value # Load a relocatable 32-bit value
intrinsic("load_reloc_const_intel", dest_comp=1, bit_sizes=[32], intrinsic("load_reloc_const_intel", dest_comp=1, bit_sizes=[32],
indices=[PARAM_IDX], flags=[CAN_ELIMINATE, CAN_REORDER]) indices=[PARAM_IDX, BASE], flags=[CAN_ELIMINATE, CAN_REORDER])
# 1 component 32bit surface index that can be used for bindless or BTI heaps # 1 component 32bit surface index that can be used for bindless or BTI heaps
# #

2
src/intel/compiler/brw_eu.h
View file

@ -1566,7 +1566,7 @@ void
brw_MOV_reloc_imm(struct brw_codegen *p, brw_MOV_reloc_imm(struct brw_codegen *p,
struct brw_reg dst, struct brw_reg dst,
enum brw_reg_type src_type, enum brw_reg_type src_type,
uint32_t id); uint32_t id, uint32_t base);
unsigned unsigned
brw_num_sources_from_inst(const struct brw_isa_info *isa, brw_num_sources_from_inst(const struct brw_isa_info *isa,

5
src/intel/compiler/brw_eu_emit.c
View file

@ -2117,13 +2117,14 @@ void
brw_MOV_reloc_imm(struct brw_codegen *p, brw_MOV_reloc_imm(struct brw_codegen *p,
struct brw_reg dst, struct brw_reg dst,
enum brw_reg_type src_type, enum brw_reg_type src_type,
uint32_t id) uint32_t id,
uint32_t base)
{ {
assert(brw_type_size_bytes(src_type) == 4); assert(brw_type_size_bytes(src_type) == 4);
assert(brw_type_size_bytes(dst.type) == 4); assert(brw_type_size_bytes(dst.type) == 4);
brw_add_reloc(p, id, BRW_SHADER_RELOC_TYPE_MOV_IMM, brw_add_reloc(p, id, BRW_SHADER_RELOC_TYPE_MOV_IMM,
p->next_insn_offset, 0); p->next_insn_offset, base);
brw_MOV(p, dst, retype(brw_imm_ud(DEFAULT_PATCH_IMM), src_type)); brw_MOV(p, dst, retype(brw_imm_ud(DEFAULT_PATCH_IMM), src_type));
} }

3
src/intel/compiler/brw_fs_generator.cpp
View file

@ -1168,7 +1168,8 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
case SHADER_OPCODE_MOV_RELOC_IMM: case SHADER_OPCODE_MOV_RELOC_IMM:
assert(src[0].file == BRW_IMMEDIATE_VALUE); assert(src[0].file == BRW_IMMEDIATE_VALUE);
brw_MOV_reloc_imm(p, dst, dst.type, src[0].ud); assert(src[1].file == BRW_IMMEDIATE_VALUE);
brw_MOV_reloc_imm(p, dst, dst.type, src[0].ud, src[1].ud);
break; break;
case BRW_OPCODE_HALT: case BRW_OPCODE_HALT:

5
src/intel/compiler/brw_fs_nir.cpp
View file

@ -6040,13 +6040,14 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb,
case nir_intrinsic_load_reloc_const_intel: { case nir_intrinsic_load_reloc_const_intel: {
uint32_t id = nir_intrinsic_param_idx(instr); uint32_t id = nir_intrinsic_param_idx(instr);
uint32_t base = nir_intrinsic_base(instr);
/* Emit the reloc in the smallest SIMD size to limit register usage. */ /* Emit the reloc in the smallest SIMD size to limit register usage. */
const fs_builder ubld = bld.exec_all().group(1, 0); const fs_builder ubld = bld.exec_all().group(1, 0);
fs_reg small_dest = ubld.vgrf(dest.type); fs_reg small_dest = ubld.vgrf(dest.type);
ubld.UNDEF(small_dest); ubld.UNDEF(small_dest);
ubld.exec_all().group(1, 0).emit(SHADER_OPCODE_MOV_RELOC_IMM, ubld.exec_all().group(1, 0).emit(SHADER_OPCODE_MOV_RELOC_IMM, small_dest,
small_dest, brw_imm_ud(id)); brw_imm_ud(id), brw_imm_ud(base));
/* Copy propagation will get rid of this MOV. */ /* Copy propagation will get rid of this MOV. */
bld.MOV(dest, component(small_dest, 0)); bld.MOV(dest, component(small_dest, 0));