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https://gitlab.freedesktop.org/mesa/mesa.git
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cell: more instruction scheduling optimizations (MIN/MAX/LERP/etc)
Also, optimize register->memory stores.
This commit is contained in:
Brian Paul
parent
2a6c6fe01e
commit
ecac7996d4
1 changed files with 145 additions and 66 deletions
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@ -77,7 +77,7 @@ struct codegen
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/** Per-instruction temps / intermediate temps */
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int num_itemps;
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int itemps[10];
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int itemps[12];
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/** Current IF/ELSE/ENDIF nesting level */
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int if_nesting;
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@ -167,6 +167,37 @@ get_exec_mask_reg(struct codegen *gen)
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}
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static boolean
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is_register_src(struct codegen *gen, int channel,
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const struct tgsi_full_src_register *src)
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{
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int swizzle = tgsi_util_get_full_src_register_extswizzle(src, channel);
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int sign_op = tgsi_util_get_full_src_register_sign_mode(src, channel);
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if (swizzle > TGSI_SWIZZLE_W || sign_op != TGSI_UTIL_SIGN_KEEP) {
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return FALSE;
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}
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if (src->SrcRegister.File == TGSI_FILE_TEMPORARY ||
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src->SrcRegister.File == TGSI_FILE_IMMEDIATE) {
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return TRUE;
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}
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return FALSE;
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}
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static boolean
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is_memory_dst(struct codegen *gen, int channel,
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const struct tgsi_full_dst_register *dst)
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{
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if (dst->DstRegister.File == TGSI_FILE_OUTPUT) {
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return TRUE;
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}
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else {
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return FALSE;
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}
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}
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/**
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* Return the index of the SPU temporary containing the named TGSI
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* source register. If the TGSI register is a TGSI_FILE_TEMPORARY we
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@ -226,11 +257,6 @@ get_src_reg(struct codegen *gen,
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spe_lqd(gen->f, reg, gen->constants_reg, offset * 16);
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}
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break;
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case TGSI_FILE_SAMPLER:
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{
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reg = 3; /* XXX total hack */
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}
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break;
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default:
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assert(0);
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}
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@ -257,7 +283,7 @@ get_src_reg(struct codegen *gen,
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}
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/* mask with bit 31 set, the rest cleared */
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spe_load_int(gen->f, bit31mask_reg, (1 << 31));
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spe_load_uint(gen->f, bit31mask_reg, (1 << 31));
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if (sign_op == TGSI_UTIL_SIGN_CLEAR) {
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spe_andc(gen->f, result_reg, reg, bit31mask_reg);
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@ -434,6 +460,7 @@ static boolean
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emit_MOV(struct codegen *gen, const struct tgsi_full_instruction *inst)
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{
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int ch, src_reg[4], dst_reg[4];
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spe_comment(gen->f, -4, "MOV:");
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for (ch = 0; ch < 4; ch++) {
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if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << ch)) {
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@ -441,11 +468,18 @@ emit_MOV(struct codegen *gen, const struct tgsi_full_instruction *inst)
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dst_reg[ch] = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
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}
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}
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for (ch = 0; ch < 4; ch++) {
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if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << ch)) {
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/* XXX we don't always need to actually emit a mov instruction here */
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spe_move(gen->f, dst_reg[ch], src_reg[ch]);
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store_dest_reg(gen, dst_reg[ch], ch, &inst->FullDstRegisters[0]);
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if (is_register_src(gen, ch, &inst->FullSrcRegisters[0]) &&
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is_memory_dst(gen, ch, &inst->FullDstRegisters[0])) {
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/* special-case: register to memory store */
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store_dest_reg(gen, src_reg[ch], ch, &inst->FullDstRegisters[0]);
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}
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else {
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spe_move(gen->f, dst_reg[ch], src_reg[ch]);
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store_dest_reg(gen, dst_reg[ch], ch, &inst->FullDstRegisters[0]);
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}
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free_itemps(gen);
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}
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}
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@ -546,23 +580,37 @@ emit_MAD(struct codegen *gen, const struct tgsi_full_instruction *inst)
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static boolean
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emit_LERP(struct codegen *gen, const struct tgsi_full_instruction *inst)
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{
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int ch;
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int tmp_reg = get_itemp(gen);
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int ch, s1_reg[4], s2_reg[4], s3_reg[4], d_reg[4], tmp_reg[4];
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spe_comment(gen->f, -4, "LERP:");
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/* setup/get src/dst/temp regs */
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for (ch = 0; ch < 4; ch++) {
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if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << ch)) {
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int s1_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
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int s2_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[1]);
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int s3_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[2]);
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int d_reg = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
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/* d = s3 + s1(s2 - s3) */
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spe_fs(gen->f, tmp_reg, s2_reg, s3_reg);
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spe_fma(gen->f, d_reg, tmp_reg, s1_reg, s3_reg);
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store_dest_reg(gen, d_reg, ch, &inst->FullDstRegisters[0]);
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free_itemps(gen);
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s1_reg[ch] = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
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s2_reg[ch] = get_src_reg(gen, ch, &inst->FullSrcRegisters[1]);
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s3_reg[ch] = get_src_reg(gen, ch, &inst->FullSrcRegisters[2]);
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d_reg[ch] = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
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tmp_reg[ch] = get_itemp(gen);
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}
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}
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/* d = s3 + s1(s2 - s3) */
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/* do all subtracts, then all fma, then all stores to better pipeline */
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for (ch = 0; ch < 4; ch++) {
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if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << ch)) {
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spe_fs(gen->f, tmp_reg[ch], s2_reg[ch], s3_reg[ch]);
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}
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}
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for (ch = 0; ch < 4; ch++) {
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if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << ch)) {
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spe_fma(gen->f, d_reg[ch], tmp_reg[ch], s1_reg[ch], s3_reg[ch]);
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}
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}
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for (ch = 0; ch < 4; ch++) {
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if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << ch)) {
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store_dest_reg(gen, d_reg[ch], ch, &inst->FullDstRegisters[0]);
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}
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}
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free_itemps(gen);
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return true;
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}
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@ -651,7 +699,7 @@ emit_ABS(struct codegen *gen, const struct tgsi_full_instruction *inst)
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const int bit31mask_reg = get_itemp(gen);
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/* mask with bit 31 set, the rest cleared */
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spe_load_int(gen->f, bit31mask_reg, (1 << 31));
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spe_load_uint(gen->f, bit31mask_reg, (1 << 31));
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/* d = sign bit cleared in s1 */
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spe_andc(gen->f, d_reg, s1_reg, bit31mask_reg);
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@ -714,35 +762,41 @@ static boolean
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emit_DP4(struct codegen *gen, const struct tgsi_full_instruction *inst)
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{
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int ch;
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int s0x_reg, s0y_reg, s0z_reg, s0w_reg;
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int s1x_reg, s1y_reg, s1z_reg, s1w_reg;
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int t0_reg = get_itemp(gen), t1_reg = get_itemp(gen);
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spe_comment(gen->f, -4, "DP4:");
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int s1_reg = get_src_reg(gen, CHAN_X, &inst->FullSrcRegisters[0]);
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int s2_reg = get_src_reg(gen, CHAN_X, &inst->FullSrcRegisters[1]);
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int tmp_reg = get_itemp(gen);
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s0x_reg = get_src_reg(gen, CHAN_X, &inst->FullSrcRegisters[0]);
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s1x_reg = get_src_reg(gen, CHAN_X, &inst->FullSrcRegisters[1]);
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s0y_reg = get_src_reg(gen, CHAN_Y, &inst->FullSrcRegisters[0]);
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s1y_reg = get_src_reg(gen, CHAN_Y, &inst->FullSrcRegisters[1]);
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s0z_reg = get_src_reg(gen, CHAN_Z, &inst->FullSrcRegisters[0]);
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s1z_reg = get_src_reg(gen, CHAN_Z, &inst->FullSrcRegisters[1]);
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s0w_reg = get_src_reg(gen, CHAN_W, &inst->FullSrcRegisters[0]);
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s1w_reg = get_src_reg(gen, CHAN_W, &inst->FullSrcRegisters[1]);
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/* t = x0 * x1 */
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spe_fm(gen->f, tmp_reg, s1_reg, s2_reg);
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/* t0 = x0 * x1 */
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spe_fm(gen->f, t0_reg, s0x_reg, s1x_reg);
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s1_reg = get_src_reg(gen, CHAN_Y, &inst->FullSrcRegisters[0]);
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s2_reg = get_src_reg(gen, CHAN_Y, &inst->FullSrcRegisters[1]);
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/* t = y0 * y1 + t */
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spe_fma(gen->f, tmp_reg, s1_reg, s2_reg, tmp_reg);
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/* t1 = y0 * y1 */
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spe_fm(gen->f, t1_reg, s0y_reg, s1y_reg);
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s1_reg = get_src_reg(gen, CHAN_Z, &inst->FullSrcRegisters[0]);
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s2_reg = get_src_reg(gen, CHAN_Z, &inst->FullSrcRegisters[1]);
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/* t = z0 * z1 + t */
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spe_fma(gen->f, tmp_reg, s1_reg, s2_reg, tmp_reg);
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/* t0 = z0 * z1 + t0 */
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spe_fma(gen->f, t0_reg, s0z_reg, s1z_reg, t0_reg);
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s1_reg = get_src_reg(gen, CHAN_W, &inst->FullSrcRegisters[0]);
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s2_reg = get_src_reg(gen, CHAN_W, &inst->FullSrcRegisters[1]);
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/* t = w0 * w1 + t */
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spe_fma(gen->f, tmp_reg, s1_reg, s2_reg, tmp_reg);
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/* t1 = w0 * w1 + t1 */
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spe_fma(gen->f, t1_reg, s0w_reg, s1w_reg, t1_reg);
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/* t0 = t0 + t1 */
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spe_fa(gen->f, t0_reg, t0_reg, t1_reg);
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for (ch = 0; ch < 4; ch++) {
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if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << ch)) {
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int d_reg = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
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spe_move(gen->f, d_reg, tmp_reg);
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store_dest_reg(gen, tmp_reg, ch, &inst->FullDstRegisters[0]);
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spe_move(gen->f, d_reg, t0_reg);
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store_dest_reg(gen, d_reg, ch, &inst->FullDstRegisters[0]);
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}
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}
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@ -756,6 +810,7 @@ emit_DP4(struct codegen *gen, const struct tgsi_full_instruction *inst)
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static boolean
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emit_DPH(struct codegen *gen, const struct tgsi_full_instruction *inst)
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{
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/* XXX rewrite this function to look more like DP3/DP4 */
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int ch;
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spe_comment(gen->f, -4, "DPH:");
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@ -1357,26 +1412,38 @@ emit_TXP(struct codegen *gen, const struct tgsi_full_instruction *inst)
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static boolean
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emit_MAX(struct codegen *gen, const struct tgsi_full_instruction *inst)
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{
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int ch;
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int ch, s0_reg[4], s1_reg[4], d_reg[4], tmp_reg[4];
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spe_comment(gen->f, -4, "MAX:");
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for (ch = 0; ch < 4; ch++) {
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if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << ch)) {
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int s1_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
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int s2_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[1]);
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int d_reg = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
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int tmp_reg = get_itemp(gen);
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/* d = (s1 > s2) ? s1 : s2 */
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spe_fcgt(gen->f, tmp_reg, s1_reg, s2_reg);
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spe_selb(gen->f, d_reg, s2_reg, s1_reg, tmp_reg);
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store_dest_reg(gen, d_reg, ch, &inst->FullDstRegisters[0]);
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free_itemps(gen);
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s0_reg[ch] = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
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s1_reg[ch] = get_src_reg(gen, ch, &inst->FullSrcRegisters[1]);
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d_reg[ch] = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
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tmp_reg[ch] = get_itemp(gen);
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}
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}
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/* d = (s0 > s1) ? s0 : s1 */
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for (ch = 0; ch < 4; ch++) {
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if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << ch)) {
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spe_fcgt(gen->f, tmp_reg[ch], s0_reg[ch], s1_reg[ch]);
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}
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}
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for (ch = 0; ch < 4; ch++) {
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if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << ch)) {
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spe_selb(gen->f, d_reg[ch], s1_reg[ch], s0_reg[ch], tmp_reg[ch]);
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}
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}
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for (ch = 0; ch < 4; ch++) {
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if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << ch)) {
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store_dest_reg(gen, d_reg[ch], ch, &inst->FullDstRegisters[0]);
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}
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}
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free_itemps(gen);
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return true;
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}
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@ -1386,26 +1453,38 @@ emit_MAX(struct codegen *gen, const struct tgsi_full_instruction *inst)
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static boolean
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emit_MIN(struct codegen *gen, const struct tgsi_full_instruction *inst)
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{
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int ch;
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int ch, s0_reg[4], s1_reg[4], d_reg[4], tmp_reg[4];
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spe_comment(gen->f, -4, "MIN:");
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for (ch = 0; ch < 4; ch++) {
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if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << ch)) {
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int s1_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
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int s2_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[1]);
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int d_reg = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
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int tmp_reg = get_itemp(gen);
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/* d = (s2 > s1) ? s1 : s2 */
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spe_fcgt(gen->f, tmp_reg, s2_reg, s1_reg);
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spe_selb(gen->f, d_reg, s2_reg, s1_reg, tmp_reg);
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store_dest_reg(gen, d_reg, ch, &inst->FullDstRegisters[0]);
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free_itemps(gen);
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s0_reg[ch] = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
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s1_reg[ch] = get_src_reg(gen, ch, &inst->FullSrcRegisters[1]);
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d_reg[ch] = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
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tmp_reg[ch] = get_itemp(gen);
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}
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}
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/* d = (s1 > s0) ? s0 : s1 */
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for (ch = 0; ch < 4; ch++) {
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if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << ch)) {
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spe_fcgt(gen->f, tmp_reg[ch], s1_reg[ch], s0_reg[ch]);
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}
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}
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for (ch = 0; ch < 4; ch++) {
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if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << ch)) {
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spe_selb(gen->f, d_reg[ch], s1_reg[ch], s0_reg[ch], tmp_reg[ch]);
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}
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}
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for (ch = 0; ch < 4; ch++) {
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if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << ch)) {
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store_dest_reg(gen, d_reg[ch], ch, &inst->FullDstRegisters[0]);
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}
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}
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free_itemps(gen);
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return true;
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}
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