From ec9d357b33a490e6325215052aa2bb3175e05cf8 Mon Sep 17 00:00:00 2001 From: Qiang Yu Date: Mon, 6 Jun 2022 16:37:16 +0800 Subject: [PATCH] radeonsi: implement nir_intrinsic_load_half_line_width_amd MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reviewed-by: Marek Olšák Signed-off-by: Qiang Yu Part-of: --- src/gallium/drivers/radeonsi/si_shader_llvm.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/gallium/drivers/radeonsi/si_shader_llvm.c b/src/gallium/drivers/radeonsi/si_shader_llvm.c index 1dc2c1fac50..300a8db6305 100644 --- a/src/gallium/drivers/radeonsi/si_shader_llvm.c +++ b/src/gallium/drivers/radeonsi/si_shader_llvm.c @@ -796,6 +796,13 @@ static LLVMValueRef si_llvm_load_intrinsic(struct ac_shader_abi *abi, nir_intrin case nir_intrinsic_load_ring_es2gs_offset_amd: return ac_get_arg(&ctx->ac, ctx->args.es2gs_offset); + case nir_intrinsic_load_clip_half_line_width_amd: { + LLVMValueRef ptr = + LLVMBuildPointerCast(ctx->ac.builder, ac_get_arg(&ctx->ac, ctx->small_prim_cull_info), + LLVMPointerType(ctx->ac.v2f32, AC_ADDR_SPACE_CONST_32BIT), ""); + return ac_build_load_to_sgpr(&ctx->ac, ptr, LLVMConstInt(ctx->ac.i32, 4, 0)); + } + default: return NULL; }