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radv: fix formatting

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Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23719>
This commit is contained in:
Eric Engestrom 2023-06-19 11:19:33 +01:00
parent 45a0de8491
commit ec8932fd63
4 changed files with 10 additions and 13 deletions
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3
src/amd/vulkan/radv_cp_reg_shadowing.c
View file

@ -113,8 +113,7 @@ radv_emit_shadow_regs_preamble(struct radeon_cmdbuf *cs, const struct radv_devic
{
struct radeon_winsys *ws = device->ws;
ws->cs_execute_ib(cs, queue_state->shadow_regs_ib, 0,
queue_state->shadow_regs_ib_size_dw & 0xffff);
ws->cs_execute_ib(cs, queue_state->shadow_regs_ib, 0, queue_state->shadow_regs_ib_size_dw & 0xffff);
radv_cs_add_buffer(device->ws, cs, queue_state->shadowed_regs);
radv_cs_add_buffer(device->ws, cs, queue_state->shadow_regs_ib);

3
src/amd/vulkan/radv_device.c
View file

@ -783,8 +783,7 @@ radv_CreateDevice(VkPhysicalDevice physicalDevice, const VkDeviceCreateInfo *pCr
device->overallocation_disallowed = overallocation_disallowed;
mtx_init(&device->overallocation_mutex, mtx_plain);
if (physical_device->rad_info.register_shadowing_required ||
device->instance->debug_flags & RADV_DEBUG_SHADOW_REGS)
if (physical_device->rad_info.register_shadowing_required || device->instance->debug_flags & RADV_DEBUG_SHADOW_REGS)
device->uses_shadow_regs = true;
/* Create one context per queue priority. */

4
src/amd/vulkan/radv_radeon_winsys.h
View file

@ -303,8 +303,8 @@ struct radeon_winsys {
void (*cs_execute_secondary)(struct radeon_cmdbuf *parent, struct radeon_cmdbuf *child, bool allow_ib2);
void (*cs_execute_ib)(struct radeon_cmdbuf *cs, struct radeon_winsys_bo *bo,
const uint64_t offset, const uint32_t cdw);
void (*cs_execute_ib)(struct radeon_cmdbuf *cs, struct radeon_winsys_bo *bo, const uint64_t offset,
const uint32_t cdw);
void (*cs_dump)(struct radeon_cmdbuf *cs, FILE *file, const int *trace_ids, int trace_id_count);

13
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
View file

@ -721,8 +721,8 @@ radv_amdgpu_cs_execute_secondary(struct radeon_cmdbuf *_parent, struct radeon_cm
}
static void
radv_amdgpu_cs_execute_ib(struct radeon_cmdbuf *_cs, struct radeon_winsys_bo *bo,
const uint64_t offset, const uint32_t cdw)
radv_amdgpu_cs_execute_ib(struct radeon_cmdbuf *_cs, struct radeon_winsys_bo *bo, const uint64_t offset,
const uint32_t cdw)
{
struct radv_amdgpu_cs *cs = radv_amdgpu_cs(_cs);
const uint64_t va = bo->va + offset;
@ -900,9 +900,8 @@ radv_assign_last_submit(struct radv_amdgpu_ctx *ctx, struct radv_amdgpu_cs_reque
}
static unsigned
radv_amdgpu_count_ibs(struct radeon_cmdbuf **cs_array, unsigned cs_count,
unsigned initial_preamble_count, unsigned continue_preamble_count,
unsigned postamble_count)
radv_amdgpu_count_ibs(struct radeon_cmdbuf **cs_array, unsigned cs_count, unsigned initial_preamble_count,
unsigned continue_preamble_count, unsigned postamble_count)
{
unsigned num_ibs = 0;
@ -929,8 +928,8 @@ radv_amdgpu_winsys_cs_submit_internal(struct radv_amdgpu_ctx *ctx, int queue_idx
struct radv_amdgpu_cs *last_cs = radv_amdgpu_cs(cs_array[cs_count - 1]);
struct radv_amdgpu_winsys *ws = last_cs->ws;
const unsigned num_ibs = radv_amdgpu_count_ibs(cs_array, cs_count, initial_preamble_count,
continue_preamble_count, postamble_count);
const unsigned num_ibs =
radv_amdgpu_count_ibs(cs_array, cs_count, initial_preamble_count, continue_preamble_count, postamble_count);
const unsigned ib_array_size = MIN2(RADV_MAX_IBS_PER_SUBMIT, num_ibs);
STACK_ARRAY(struct radv_amdgpu_cs_ib_info, ibs, ib_array_size);