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nv50,nvc0: serialize between before/after using a zeta surface as color

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This happens during "3d" blit operations, where we must reinterpret it
as color in order to support stencil/depth masking. However the hardware
isn't necessarily amused by this, esp when multiple draws are queued up.
Throw in serialize calls in order to get it to flush out previous draws.

This was noticeable in the test
dEQP-GLES3.functional.fbo.invalidate.sub.unbind_blit_msaa_stencil,
although 3d blit operation had to be forced on nvc0 where it's much
rarer.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8396>
This commit is contained in:
Ilia Mirkin 2021-01-08 01:37:35 -05:00 • committed by Marge Bot
parent f763d0f195
commit ec668e2fd1
2 changed files with 31 additions and 0 deletions
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16
src/gallium/drivers/nouveau/nv50/nv50_surface.c
View file

@ -1373,6 +1373,16 @@ nv50_blit_3d(struct nv50_context *nv50, const struct pipe_blit_info *info)
nv50_state_validate_3d(nv50, ~0);
/* When flipping a surface from zeta <-> color "mode", we have to wait for
* the GPU to flush its current draws.
*/
struct nv50_miptree *mt = nv50_miptree(dst);
bool serialize = util_format_is_depth_or_stencil(info->dst.format);
if (serialize && mt->base.status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) {
BEGIN_NV04(push, SUBC_3D(NV50_GRAPH_SERIALIZE), 1);
PUSH_DATA (push, 0);
}
x_range = (float)info->src.box.width / (float)info->dst.box.width;
y_range = (float)info->src.box.height / (float)info->dst.box.height;
@ -1475,6 +1485,12 @@ nv50_blit_3d(struct nv50_context *nv50, const struct pipe_blit_info *info)
BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
PUSH_DATA (push, 1);
/* mark the surface as reading, which will force a serialize next time it's
* used for writing.
*/
if (serialize)
mt->base.status |= NOUVEAU_BUFFER_STATUS_GPU_READING;
nv50_blitctx_post_blit(blit);
}

15
src/gallium/drivers/nouveau/nvc0/nvc0_surface.c
View file

@ -1239,9 +1239,19 @@ nvc0_blit_3d(struct nvc0_context *nvc0, const struct pipe_blit_info *info)
}
}
bool serialize = false;
struct nv50_miptree *mt = nv50_miptree(dst);
if (screen->eng3d->oclass >= TU102_3D_CLASS) {
IMMED_NVC0(push, SUBC_3D(TU102_3D_SET_COLOR_RENDER_TO_ZETA_SURFACE),
util_format_is_depth_or_stencil(info->dst.format));
} else {
/* When flipping a surface from zeta <-> color "mode", we have to wait for
* the GPU to flush its current draws.
*/
serialize = util_format_is_depth_or_stencil(info->dst.format);
if (serialize && mt->base.status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) {
IMMED_NVC0(push, NVC0_3D(SERIALIZE), 0);
}
}
IMMED_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 0);
@ -1386,6 +1396,11 @@ nvc0_blit_3d(struct nvc0_context *nvc0, const struct pipe_blit_info *info)
IMMED_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
if (screen->eng3d->oclass >= TU102_3D_CLASS)
IMMED_NVC0(push, SUBC_3D(TU102_3D_SET_COLOR_RENDER_TO_ZETA_SURFACE), 0);
else if (serialize)
/* mark the surface as reading, which will force a serialize next time
* it's used for writing.
*/
mt->base.status |= NOUVEAU_BUFFER_STATUS_GPU_READING;
}
static void