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tu, ir3, nir: Plumb through driver param for alpha-to-coverage

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We will need this when alpha-to-coverage is dynamic and we need to
emulate it.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39335>
This commit is contained in:
Connor Abbott 2025-12-31 13:07:49 -05:00 • committed by Marge Bot
parent 22a061fb91
commit ec37fed52b
7 changed files with 20 additions and 5 deletions
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1
src/compiler/nir/nir_divergence_analysis.c
View file

@ -364,6 +364,7 @@ visit_intrinsic(nir_intrinsic_instr *instr, struct divergence_state *state)
case nir_intrinsic_load_ray_query_global_intel:
case nir_intrinsic_load_call_return_address_amd:
case nir_intrinsic_load_indirect_address_intel:
case nir_intrinsic_load_alpha_to_coverage_enable_ir3:
is_divergent = false;
break;

1
src/compiler/nir/nir_intrinsics.py
View file

@ -1537,6 +1537,7 @@ intrinsic("load_frag_coord_unscaled_ir3", dest_comp=4,
flags=[CAN_ELIMINATE, CAN_REORDER], bit_sizes=[32])
intrinsic("load_frag_coord_gmem_ir3", dest_comp=4,
flags=[CAN_ELIMINATE, CAN_REORDER], bit_sizes=[32])
system_value("alpha_to_coverage_enable_ir3", 1)
# Per-view gl_FragSizeEXT and gl_FragCoord offset.
intrinsic("load_frag_size_ir3", src_comp=[1], dest_comp=2, indices=[RANGE],

3
src/freedreno/ir3/ir3_compiler_nir.c
View file

@ -3217,6 +3217,9 @@ emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr)
case nir_intrinsic_load_frag_invocation_count:
dst[0] = create_driver_param(ctx, IR3_DP_FS(frag_invocation_count));
break;
case nir_intrinsic_load_alpha_to_coverage_enable_ir3:
dst[0] = create_driver_param(ctx, IR3_DP_FS(alpha_to_coverage_enable));
break;
case nir_intrinsic_load_frag_size_ir3:
case nir_intrinsic_load_frag_offset_ir3:
case nir_intrinsic_load_gmem_frag_scale_ir3:

3
src/freedreno/ir3/ir3_nir.c
View file

@ -1761,6 +1761,9 @@ ir3_get_driver_param_info(const nir_shader *shader, nir_intrinsic_instr *intr,
case nir_intrinsic_load_frag_invocation_count:
param_info->offset = IR3_DP_FS(frag_invocation_count);
break;
case nir_intrinsic_load_alpha_to_coverage_enable_ir3:
param_info->offset = IR3_DP_FS(alpha_to_coverage_enable);
break;
default:
return false;
}

3
src/freedreno/ir3/ir3_shader.h
View file

@ -103,7 +103,8 @@ struct ir3_driver_params_fs {
/* Dynamic params (that aren't known when compiling the shader) */
#define IR3_DP_FS_DYNAMIC dword_offsetof(struct ir3_driver_params_fs, frag_invocation_count)
uint32_t frag_invocation_count;
uint32_t __pad_05_07[3];
uint32_t alpha_to_coverage_enable;
uint32_t __pad_06_07[2];
uint32_t frag_size;
uint32_t __pad_09;
uint32_t frag_offset;

4
src/freedreno/vulkan/tu_cmd_buffer.cc
View file

@ -7866,7 +7866,7 @@ tu_emit_fdm_params(struct tu_cmd_buffer *cmd,
STATIC_ASSERT(IR3_DP_FS(frag_invocation_count) == IR3_DP_FS_DYNAMIC);
tu_cs_emit(cs, fs->fs.sample_shading ?
cmd->vk.dynamic_graphics_state.ms.rasterization_samples : 1);
tu_cs_emit(cs, 0);
tu_cs_emit(cs, cmd->vk.dynamic_graphics_state.ms.alpha_to_coverage_enable);
tu_cs_emit(cs, 0);
tu_cs_emit(cs, 0);
@ -8229,6 +8229,8 @@ tu6_draw_common(struct tu_cmd_buffer *cmd,
bool dirty_fs_params = false;
if (BITSET_TEST(cmd->vk.dynamic_graphics_state.dirty,
MESA_VK_DYNAMIC_MS_RASTERIZATION_SAMPLES) ||
BITSET_TEST(cmd->vk.dynamic_graphics_state.dirty,
MESA_VK_DYNAMIC_MS_ALPHA_TO_COVERAGE_ENABLE) ||
(cmd->state.dirty & (TU_CMD_DIRTY_PROGRAM | TU_CMD_DIRTY_FDM))) {
tu_emit_fs_params(cmd);
dirty_fs_params = true;

10
src/freedreno/vulkan/tu_shader.cc
View file

@ -678,14 +678,18 @@ lower_intrinsic(nir_builder *b, nir_intrinsic_instr *instr,
nir_def_replace(&instr->def, result);
return true;
}
case nir_intrinsic_load_frag_invocation_count: {
case nir_intrinsic_load_frag_invocation_count:
case nir_intrinsic_load_alpha_to_coverage_enable_ir3: {
if (!dev->compiler->info->props.load_shader_consts_via_preamble)
return false;
unsigned offset =
instr->intrinsic == nir_intrinsic_load_frag_invocation_count ?
IR3_DP_FS(frag_invocation_count) :
IR3_DP_FS(alpha_to_coverage_enable);
nir_def *result =
ir3_load_driver_ubo(b, 1, &shader->const_state.fdm_ubo,
IR3_DP_FS(frag_invocation_count) -
IR3_DP_FS_DYNAMIC);
offset - IR3_DP_FS_DYNAMIC);
nir_def_replace(&instr->def, result);
return true;