From ec15373268e0719823406ec7125245e023c81c5a Mon Sep 17 00:00:00 2001 From: Jose Maria Casanova Crespo Date: Fri, 10 Apr 2026 12:55:50 +0200 Subject: [PATCH] broadcom/compiler: really enable branch in delay slots validation The validation of branch instructions happening in branch and thrsw delay slots has been dead code since it was introduced as the check was after: if (inst->type != V3D_QPU_INSTR_TYPE_ALU) return; Now last_branch_ip is updated and checks in_branch_delay_slots() are active. Fixes in_branch_delay_slots, as for branch there are always 3 delay slots. As scheduler enforces this restrictions shader-db does not show any regression. Assisted-by: Claude Opus 4.6 Fixes: 90269ba35333 ("broadcom/vc5: Use THRSW to enable multi-threaded shaders.") Reviewed-by: Iago Toral Quiroga (cherry picked from commit dd6e7c8ef07f2af067ebfd32f412214936bc6b66) Part-of: --- .pick_status.json | 2 +- src/broadcom/compiler/qpu_validate.c | 20 ++++++++++---------- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/.pick_status.json b/.pick_status.json index 1a8396c5050..b41848ed2aa 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -6404,7 +6404,7 @@ "description": "broadcom/compiler: really enable branch in delay slots validation", "nominated": true, "nomination_type": 2, - "resolution": 0, + "resolution": 1, "main_sha": null, "because_sha": "90269ba353333be13e54549ecff3adb8803661db", "notes": null diff --git a/src/broadcom/compiler/qpu_validate.c b/src/broadcom/compiler/qpu_validate.c index ec7c79d5eb3..400ba85f29b 100644 --- a/src/broadcom/compiler/qpu_validate.c +++ b/src/broadcom/compiler/qpu_validate.c @@ -81,7 +81,7 @@ fail_instr(struct v3d_qpu_validate_state *state, const char *msg) static bool in_branch_delay_slots(struct v3d_qpu_validate_state *state) { - return (state->ip - state->last_branch_ip) < 3; + return (state->ip - state->last_branch_ip) < 4; } static bool @@ -130,8 +130,16 @@ qpu_validate_inst(struct v3d_qpu_validate_state *state, struct qinst *qinst) fail_instr(state, "Implicit branch MSF read after TLB Z write"); } - if (inst->type != V3D_QPU_INSTR_TYPE_ALU) + if (inst->type == V3D_QPU_INSTR_TYPE_BRANCH) { + if (in_branch_delay_slots(state)) + fail_instr(state, "branch in a branch delay slot."); + if (in_thrsw_delay_slots(state)) + fail_instr(state, "branch in a THRSW delay slot."); + state->last_branch_ip = state->ip; return; + } + + assert(inst->type == V3D_QPU_INSTR_TYPE_ALU); if (inst->alu.mul.op == V3D_QPU_M_MULTOP) state->rtop_valid = true; @@ -383,14 +391,6 @@ qpu_validate_inst(struct v3d_qpu_validate_state *state, struct qinst *qinst) state->rtop_hazard = true; state->rtop_valid = false; } - - if (inst->type == V3D_QPU_INSTR_TYPE_BRANCH) { - if (in_branch_delay_slots(state)) - fail_instr(state, "branch in a branch delay slot."); - if (in_thrsw_delay_slots(state)) - fail_instr(state, "branch in a THRSW delay slot."); - state->last_branch_ip = state->ip; - } } static void