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Revert "iris: slow clear higher miplevels on single sampled 8bpp resources that have TILE64"

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Miptails are now disabled on Tile64 resources, so we can drop this
restriction.

Ref: e3a5ade9 ('intel/isl: Disable miptails to align LODs for CCS WA')

This reverts commit 8670fd6ac4.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28984>
This commit is contained in:
Rohan Garg 2024-04-30 13:31:24 +02:00 • committed by Marge Bot
parent 9e66d89be9
commit ec06911b3d
1 changed files with 0 additions and 12 deletions
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12
src/gallium/drivers/iris/iris_clear.c
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@ -134,18 +134,6 @@ can_fast_clear_color(struct iris_context *ice,
*/
if (level > 0 && util_format_get_blocksizebits(p_res->format) == 8 &&
p_res->width0 % 64) {
assert(res->surf.samples == 1);
return false;
}
/* TODO: Fast clearing higher miplevels on 8 bpp single sampled TILE64
* resources for certain widths seems broken.
*/
if (level > 0 && util_format_get_blocksizebits(p_res->format) == 8 &&
res->surf.tiling == ISL_TILING_64) {
assert(res->surf.samples == 1);
perf_debug(&ice->dbg, "Slow clearing higher miplevels for single sampled "
"8 bpp resource");
return false;
}