From ec0646a0b3572c7b217ea17908c755a95265ed9e Mon Sep 17 00:00:00 2001
From: Constantine Shablia <constantine.shablya@collabora.com>
Date: Fri, 18 Oct 2024 17:25:34 +0200
Subject: [PATCH] pan/va: Define the TEX_GRADIENT instruction

Define the TEX_GRADIENT instruction in valhall/ISA.xml, and add the
necessary bits to the compiler to expose it.

Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31742>
---
 src/panfrost/compiler/bir.c             |  1 +
 src/panfrost/compiler/compiler.h        |  4 ++++
 src/panfrost/compiler/valhall/ISA.xml   | 24 ++++++++++++++++++++++++
 src/panfrost/compiler/valhall/va_pack.c | 17 +++++++++++++++--
 4 files changed, 44 insertions(+), 2 deletions(-)

diff --git a/src/panfrost/compiler/bir.c b/src/panfrost/compiler/bir.c
index 5836c5d4ff3..9520eb8af3b 100644
--- a/src/panfrost/compiler/bir.c
+++ b/src/panfrost/compiler/bir.c
@@ -114,6 +114,7 @@ bi_count_write_registers(const bi_instr *ins, unsigned d)
 
       case BI_OPCODE_TEX_SINGLE:
       case BI_OPCODE_TEX_FETCH:
+      case BI_OPCODE_TEX_GRADIENT:
       case BI_OPCODE_TEX_GATHER: {
          unsigned chans = util_bitcount(ins->write_mask);
 
diff --git a/src/panfrost/compiler/compiler.h b/src/panfrost/compiler/compiler.h
index 8c1cffe2b57..9dc342a76fa 100644
--- a/src/panfrost/compiler/compiler.h
+++ b/src/panfrost/compiler/compiler.h
@@ -508,6 +508,10 @@ typedef struct {
          bool texel_offset;
          bool array_enable;
          bool integer_coordinates;
+         bool derivative_enable;
+         bool force_delta_enable;
+         bool lod_bias_disable;
+         bool lod_clamp_disable;
          enum bi_fetch_component fetch_component;
          enum bi_va_lod_mode va_lod_mode;
          enum bi_dimension dimension;
diff --git a/src/panfrost/compiler/valhall/ISA.xml b/src/panfrost/compiler/valhall/ISA.xml
index 12d67817aa3..5bdecf2a8cd 100644
--- a/src/panfrost/compiler/valhall/ISA.xml
+++ b/src/panfrost/compiler/valhall/ISA.xml
@@ -2518,6 +2518,30 @@
     <immediate name="sr_count" size="4" pseudo="true"/>
   </ins>
 
+  <ins name="TEX_GRADIENT" title="Texture gradient" opcode="0x12A" message="tex" unit="T">
+    <desc>Texture sample with explicit gradient.</desc>
+    <slot/>
+    <skip/>
+    <register_type/>
+    <register_width/>
+    <write_mask/>
+    <dimension/>
+    <wide_indices/>
+    <force_delta_enable/>
+    <lod_bias_disable/>
+    <lod_clamp_disable/>
+    <derivative_enable/>
+
+    <sr_count/>
+    <sr_write_count/>
+
+    <sr write="true" flags="false"/>
+    <sr read="true" flags="false"/>
+    <src size="64">Image to read from</src>
+    <src pseudo="true">Dummy for IR</src>
+    <immediate name="sr_count" size="4" pseudo="true"/>
+  </ins>
+
   <ins name="TEX_DUAL" title="Dual texture" opcode="0x12F" unused="true" unit="T">
     <desc>Pair of texture instructions.</desc>
     <slot/>
diff --git a/src/panfrost/compiler/valhall/va_pack.c b/src/panfrost/compiler/valhall/va_pack.c
index 38e09585b79..89a653967a5 100644
--- a/src/panfrost/compiler/valhall/va_pack.c
+++ b/src/panfrost/compiler/valhall/va_pack.c
@@ -904,14 +904,16 @@ va_pack_instr(const bi_instr *I)
       break;
    }
 
+   case BI_OPCODE_TEX_GRADIENT:
    case BI_OPCODE_TEX_SINGLE:
    case BI_OPCODE_TEX_FETCH:
    case BI_OPCODE_TEX_GATHER: {
       /* Image to read from */
       hex |= ((uint64_t)va_pack_src(I, 1)) << 0;
 
-      if (I->op == BI_OPCODE_TEX_FETCH && I->shadow)
-         invalid_instruction(I, "TEX_FETCH does not support .shadow");
+      if ((I->op == BI_OPCODE_TEX_FETCH || I->op == BI_OPCODE_TEX_GRADIENT) &&
+          I->shadow)
+         invalid_instruction(I, "texture instruction does not support .shadow");
 
       if (I->wide_indices)
          hex |= (1ull << 8);
@@ -926,6 +928,17 @@ va_pack_instr(const bi_instr *I)
       if (!bi_is_regfmt_16(I->register_format))
          hex |= (1ull << 46);
 
+      if (I->op == BI_OPCODE_TEX_GRADIENT) {
+         if (I->force_delta_enable)
+            hex |= (1ull << 12);
+         if (I->lod_bias_disable)
+            hex |= (1ull << 13);
+         if (I->lod_clamp_disable)
+            hex |= (1ull << 14);
+         if (I->derivative_enable)
+            hex |= (1ull << 15);
+      }
+
       if (I->op == BI_OPCODE_TEX_SINGLE)
          hex |= ((uint64_t)va_pack_lod_mode(I)) << 13;