diff --git a/src/freedreno/vulkan/tu_cmd_buffer.cc b/src/freedreno/vulkan/tu_cmd_buffer.cc
index 9d503edee9b..44ebfa2633c 100644
--- a/src/freedreno/vulkan/tu_cmd_buffer.cc
+++ b/src/freedreno/vulkan/tu_cmd_buffer.cc
@@ -260,6 +260,7 @@ tu6_lazy_init_vsc(struct tu_cmd_buffer *cmd)
    cmd->vsc_draw_strm_offset = prim_strm_size;
    cmd->vsc_draw_strm_size_offset = cmd->vsc_draw_strm_offset + draw_strm_size;
    cmd->vsc_state_offset = cmd->vsc_draw_strm_size_offset + draw_strm_size_size;
+   cmd->vsc_initialized = true;
 }
 
 static void
@@ -297,8 +298,6 @@ tu_emit_vsc(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
       tu_cs_emit(cs, A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG(VSC_PIPE_DATA_PRIM_BASE));
       tu_emit_vis_stream_patchpoint(cmd, cs, cmd->vsc_prim_strm_offset);
    }
-
-   cmd->vsc_initialized = true;
 }
 
 struct tu_set_render_mode {
@@ -3532,11 +3531,11 @@ tu6_tile_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
       tu_cs_emit_regs(cs, RB_BIN_FOVEAT(CHIP));
    }
 
-   if (use_binning) {
-      if (!cmd->vsc_initialized) {
-         tu6_lazy_init_vsc(cmd);
-      }
+   if (!cmd->vsc_initialized) {
+      tu6_lazy_init_vsc(cmd);
+   }
 
+   if (use_binning) {
       /* We always emit VSC before each renderpass, because due to
        * skipsaverestore the underlying VSC registers may have become
        * invalid. Normally we'd need to WFI before setting these non-context
@@ -3597,13 +3596,6 @@ tu6_tile_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
    }
 
    if (vsc->binning_possible) {
-      /* On a7xx we always need VSC allocated because the VSC state has to go
-       * together with other stream data. We could allocate just the VSC state
-       * if binning is disabled but it doesn't seem worth it.
-       */
-      if (CHIP >= A7XX && !cmd->vsc_initialized)
-         tu6_lazy_init_vsc(cmd);
-
       /* Upload state regs to memory to be restored on skipsaverestore
        * preemption. On a7xx this is considered part of the vis stream that
        * requires a patchpoint.