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i965: Don't forget the cube map padding on gen5+.

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We had a fixup for gen4's 3d-layout cubemaps (which, iirc, we'd
experimentally found to be necessary!), but while the spec still requires
it on gen5, we'd been missing it in the array-layout cubemaps.

Cc: "9.1 9.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit 791550aa8e)
This commit is contained in:
Eric Anholt 2013-10-08 00:20:04 -07:00 • committed by Carl Worth
parent fb3e55f898
commit eb69e251a8
1 changed files with 15 additions and 7 deletions
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22
src/mesa/drivers/dri/i965/brw_tex_layout.c
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@ -204,6 +204,18 @@ brw_miptree_layout_2d(struct intel_mipmap_tree *mt)
}
}
static void
align_cube(struct intel_mipmap_tree *mt)
{
/* The 965's sampler lays cachelines out according to how accesses
* in the texture surfaces run, so they may be "vertical" through
* memory. As a result, the docs say in Surface Padding Requirements:
* Sampling Engine Surfaces that two extra rows of padding are required.
*/
if (mt->target == GL_TEXTURE_CUBE_MAP)
mt->total_height += 2;
}
static void
brw_miptree_layout_texture_array(struct brw_context *brw,
struct intel_mipmap_tree *mt)
@ -228,6 +240,8 @@ brw_miptree_layout_texture_array(struct brw_context *brw,
}
}
mt->total_height = qpitch * mt->physical_depth0;
align_cube(mt);
}
static void
@ -299,13 +313,7 @@ brw_miptree_layout_texture_3d(struct brw_context *brw,
}
}
/* The 965's sampler lays cachelines out according to how accesses
* in the texture surfaces run, so they may be "vertical" through
* memory. As a result, the docs say in Surface Padding Requirements:
* Sampling Engine Surfaces that two extra rows of padding are required.
*/
if (mt->target == GL_TEXTURE_CUBE_MAP)
mt->total_height += 2;
align_cube(mt);
}
void