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i965: Fix depth field setting in surface state for raw buffer on Gen7/8

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On Gen7/8 for RAW surface format, the depth field (surf[3]) in surface
state means [30:21] bits of number of entries which is different from
other surface format which uses [26:21] bits field.

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
This commit is contained in:
Zhenyu Wang 2015-04-07 13:48:38 +08:00
parent 6b722c390b
commit eb51c6d55f
2 changed files with 10 additions and 4 deletions
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7
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
View file

@ -238,8 +238,11 @@ gen7_emit_buffer_surface_state(struct brw_context *brw,
surf[1] = (bo ? bo->offset64 : 0) + buffer_offset; /* reloc */
surf[2] = SET_FIELD((buffer_size - 1) & 0x7f, GEN7_SURFACE_WIDTH) |
SET_FIELD(((buffer_size - 1) >> 7) & 0x3fff, GEN7_SURFACE_HEIGHT);
surf[3] = SET_FIELD(((buffer_size - 1) >> 21) & 0x3f, BRW_SURFACE_DEPTH) |
(pitch - 1);
if (surface_format == BRW_SURFACEFORMAT_RAW)
surf[3] = SET_FIELD(((buffer_size - 1) >> 21) & 0x3ff, BRW_SURFACE_DEPTH);
else
surf[3] = SET_FIELD(((buffer_size - 1) >> 21) & 0x3f, BRW_SURFACE_DEPTH);
surf[3] |= (pitch - 1);
surf[5] = SET_FIELD(GEN7_MOCS_L3, GEN7_SURFACE_MOCS);

7
src/mesa/drivers/dri/i965/gen8_surface_state.c
View file

@ -129,8 +129,11 @@ gen8_emit_buffer_surface_state(struct brw_context *brw,
surf[2] = SET_FIELD((buffer_size - 1) & 0x7f, GEN7_SURFACE_WIDTH) |
SET_FIELD(((buffer_size - 1) >> 7) & 0x3fff, GEN7_SURFACE_HEIGHT);
surf[3] = SET_FIELD(((buffer_size - 1) >> 21) & 0x3f, BRW_SURFACE_DEPTH) |
(pitch - 1);
if (surface_format == BRW_SURFACEFORMAT_RAW)
surf[3] = SET_FIELD(((buffer_size - 1) >> 21) & 0x3ff, BRW_SURFACE_DEPTH);
else
surf[3] = SET_FIELD(((buffer_size - 1) >> 21) & 0x3f, BRW_SURFACE_DEPTH);
surf[3] |= (pitch - 1);
surf[7] = SET_FIELD(HSW_SCS_RED, GEN7_SURFACE_SCS_R) |
SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
SET_FIELD(HSW_SCS_BLUE, GEN7_SURFACE_SCS_B) |