From eb382e0cef636817b3065c02cbdea7a626a6e8dd Mon Sep 17 00:00:00 2001 From: Lionel Landwerlin Date: Tue, 3 Mar 2026 11:02:52 +0200 Subject: [PATCH] anv: add drirc option to workaround missing application barriers on typed/untyped data Enable it for Horizon Forbidden West (only seems to have untyped data issue). Signed-off-by: Lionel Landwerlin Cc: mesa-stable Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14889 Reviewed-by: Ivan Briano (cherry picked from commit db964068bfc9e49e4d68638062c59fd2f5527353) Part-of: --- .pick_status.json | 2 +- src/intel/vulkan/anv_instance.c | 6 +++++ src/intel/vulkan/anv_private.h | 2 ++ src/intel/vulkan/genX_cmd_compute.c | 34 +++++++++++++++++++++++++++-- src/util/00-mesa-defaults.conf | 6 +++++ src/util/driconf.h | 8 +++++++ 6 files changed, 55 insertions(+), 3 deletions(-) diff --git a/.pick_status.json b/.pick_status.json index 60d7a855262..8f84c0c3c75 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -12034,7 +12034,7 @@ "description": "anv: add drirc option to workaround missing application barriers on typed/untyped data", "nominated": true, "nomination_type": 1, - "resolution": 0, + "resolution": 1, "main_sha": null, "because_sha": null, "notes": null diff --git a/src/intel/vulkan/anv_instance.c b/src/intel/vulkan/anv_instance.c index 11a0266aede..aa55d604fdd 100644 --- a/src/intel/vulkan/anv_instance.c +++ b/src/intel/vulkan/anv_instance.c @@ -17,6 +17,8 @@ static const driOptionDescription anv_dri_options[] = { DRI_CONF_ANV_ASSUME_FULL_SUBGROUPS(0) DRI_CONF_ANV_ASSUME_FULL_SUBGROUPS_WITH_BARRIER(false) DRI_CONF_ANV_ASSUME_FULL_SUBGROUPS_WITH_SHARED_MEMORY(false) + DRI_CONF_ANV_BARRIER_POST_TYPED_CLEAR_SHADER(false) + DRI_CONF_ANV_BARRIER_POST_UNTYPED_CLEAR_SHADER(false) DRI_CONF_ANV_DISABLE_FCV(false) DRI_CONF_ANV_ENABLE_BUFFER_COMP(false) DRI_CONF_ANV_DISABLE_DRM_AUX_MODIFIERS(false) @@ -225,6 +227,10 @@ anv_init_dri_options(struct anv_instance *instance) driQueryOptionb(&instance->dri_options, "vk_lower_terminate_to_discard"); instance->disable_xe2_drm_ccs_modifiers = driQueryOptionb(&instance->dri_options, "anv_disable_drm_ccs_modifiers"); + instance->barrier_post_typed_clear_shader = + driQueryOptionb(&instance->dri_options, "anv_barrier_post_typed_clear_shader"); + instance->barrier_post_untyped_clear_shader = + driQueryOptionb(&instance->dri_options, "anv_barrier_post_untyped_clear_shader"); if (instance->vk.app_info.engine_name && !strcmp(instance->vk.app_info.engine_name, "DXVK")) { diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h index 0b702c19bc1..2da159a3fa4 100644 --- a/src/intel/vulkan/anv_private.h +++ b/src/intel/vulkan/anv_private.h @@ -1793,6 +1793,8 @@ struct anv_instance { bool custom_border_colors_without_format; bool vf_component_packing; bool large_workgroup_non_coherent_image_workaround; + bool barrier_post_typed_clear_shader; + bool barrier_post_untyped_clear_shader; /* HW workarounds */ bool no_16bit; diff --git a/src/intel/vulkan/genX_cmd_compute.c b/src/intel/vulkan/genX_cmd_compute.c index 562acd7f70f..0a741ec5c5b 100644 --- a/src/intel/vulkan/genX_cmd_compute.c +++ b/src/intel/vulkan/genX_cmd_compute.c @@ -417,6 +417,36 @@ compute_update_async_threads_limit(struct anv_cmd_buffer *cmd_buffer, } } +static inline void +cmd_buffer_post_dispatch_wa(struct anv_cmd_buffer *cmd_buffer) +{ + genX(cmd_buffer_post_dispatch_wa)(cmd_buffer); + + struct anv_cmd_compute_state *comp_state = &cmd_buffer->state.compute; + + /* Workaround WaW hazards in applications that clear a buffer and start + * writing to it immediately without a barrier between the clear & write + * operations. + */ + if (cmd_buffer->device->physical->instance->barrier_post_typed_clear_shader && + (comp_state->shader->bind_map.inferred_behavior & ANV_PIPELINE_BEHAVIOR_CLEAR_TYPED)) { + anv_add_pending_pipe_bits(cmd_buffer, + VK_PIPELINE_STAGE_2_COMPUTE_SHADER_BIT, + VK_PIPELINE_STAGE_2_TOP_OF_PIPE_BIT, + ANV_PIPE_HDC_PIPELINE_FLUSH_BIT, + "clear shader typed L1 flush app wa"); + } + if (cmd_buffer->device->physical->instance->barrier_post_untyped_clear_shader && + (comp_state->shader->bind_map.inferred_behavior & ANV_PIPELINE_BEHAVIOR_CLEAR_UNTYPED)) { + anv_add_pending_pipe_bits(cmd_buffer, + VK_PIPELINE_STAGE_2_COMPUTE_SHADER_BIT, + VK_PIPELINE_STAGE_2_TOP_OF_PIPE_BIT, + ANV_PIPE_UNTYPED_DATAPORT_CACHE_FLUSH_BIT | + ANV_PIPE_HDC_PIPELINE_FLUSH_BIT, + "clear shader untyped L1 flush app wa"); + } +} + static inline void emit_indirect_compute_walker(struct anv_cmd_buffer *cmd_buffer, const struct brw_cs_prog_data *prog_data, @@ -467,7 +497,7 @@ emit_indirect_compute_walker(struct anv_cmd_buffer *cmd_buffer, indirect_addr.bo, 0), ); - genX(cmd_buffer_post_dispatch_wa)(cmd_buffer); + cmd_buffer_post_dispatch_wa(cmd_buffer); } static inline void @@ -535,7 +565,7 @@ emit_compute_walker(struct anv_cmd_buffer *cmd_buffer, #endif ); - genX(cmd_buffer_post_dispatch_wa)(cmd_buffer); + cmd_buffer_post_dispatch_wa(cmd_buffer); } #else /* #if GFX_VERx10 >= 125 */ diff --git a/src/util/00-mesa-defaults.conf b/src/util/00-mesa-defaults.conf index a93728b7fd3..dc263f2cb74 100644 --- a/src/util/00-mesa-defaults.conf +++ b/src/util/00-mesa-defaults.conf @@ -1125,6 +1125,12 @@ TODO: document the other workarounds. + + +