fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2025-12-23 17:40:11 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

aco: Only fix used variables to registers

Browse source 
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27137>
This commit is contained in:
Konstantin Seurer 2024-01-17 15:58:13 +01:00 • committed by Marge Bot
parent 348d13f06e
commit eb249bb18e
3 changed files with 17 additions and 3 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

16
src/amd/compiler/aco_instruction_selection.cpp
View file

@ -9308,11 +9308,13 @@ visit_intrinsic(isel_context* ctx, nir_intrinsic_instr* instr)
break;
}
case nir_intrinsic_store_scalar_arg_amd: {
BITSET_SET(ctx->output_args, nir_intrinsic_base(instr));
ctx->arg_temps[nir_intrinsic_base(instr)] =
bld.as_uniform(get_ssa_temp(ctx, instr->src[0].ssa));
break;
}
case nir_intrinsic_store_vector_arg_amd: {
BITSET_SET(ctx->output_args, nir_intrinsic_base(instr));
ctx->arg_temps[nir_intrinsic_base(instr)] =
as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
break;
@ -11668,19 +11670,27 @@ merged_wave_info_to_mask(isel_context* ctx, unsigned i)
static void
insert_rt_jump_next(isel_context& ctx, const struct ac_shader_args* args)
{
unsigned src_count = ctx.args->arg_count;
unsigned src_count = 0;
for (unsigned i = 0; i < ctx.args->arg_count; i++)
src_count += !!BITSET_TEST(ctx.output_args, i);
Pseudo_instruction* ret =
create_instruction<Pseudo_instruction>(aco_opcode::p_return, Format::PSEUDO, src_count, 0);
ctx.block->instructions.emplace_back(ret);
for (unsigned i = 0; i < src_count; i++) {
src_count = 0;
for (unsigned i = 0; i < ctx.args->arg_count; i++) {
if (!BITSET_TEST(ctx.output_args, i))
continue;
enum ac_arg_regfile file = ctx.args->args[i].file;
unsigned size = ctx.args->args[i].size;
unsigned reg = ctx.args->args[i].offset + (file == AC_ARG_SGPR ? 0 : 256);
RegClass type = RegClass(file == AC_ARG_SGPR ? RegType::sgpr : RegType::vgpr, size);
Operand op = ctx.arg_temps[i].id() ? Operand(ctx.arg_temps[i], PhysReg{reg})
: Operand(PhysReg{reg}, type);
ret->operands[i] = op;
ret->operands[src_count] = op;
src_count++;
}
Builder bld(ctx.program, ctx.block);

2
src/amd/compiler/aco_instruction_selection.h
View file

@ -106,6 +106,8 @@ struct isel_context {
/* WQM information */
uint32_t wqm_block_idx;
uint32_t wqm_instruction_idx;
BITSET_DECLARE(output_args, AC_MAX_ARGS);
};
inline Temp

2
src/amd/compiler/aco_instruction_selection_setup.cpp
View file

@ -635,6 +635,8 @@ init_context(isel_context* ctx, nir_shader* shader)
ctx->program->constant_data.insert(ctx->program->constant_data.end(),
(uint8_t*)shader->constant_data,
(uint8_t*)shader->constant_data + shader->constant_data_size);
BITSET_CLEAR_RANGE(ctx->output_args, 0, BITSET_SIZE(ctx->output_args));
}
void