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gallium/radeon: shorten render_cond variable names

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and ..._cond -> ..._invert

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák 2015-11-07 16:30:01 +01:00
parent 70c40cc989
commit eb0d3e8a90
5 changed files with 13 additions and 13 deletions
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2
src/gallium/drivers/r600/r600_state_common.c
View file

@ -1478,7 +1478,7 @@ static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info
struct pipe_draw_info info = *dinfo;
struct pipe_index_buffer ib = {};
struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
bool render_cond_bit = rctx->b.current_render_cond && !rctx->b.render_cond_force_off;
bool render_cond_bit = rctx->b.render_cond && !rctx->b.render_cond_force_off;
uint64_t mask;
if (!info.indirect && !info.count && (info.indexed || !info.count_from_stream_output)) {

6
src/gallium/drivers/radeon/r600_pipe_common.h
View file

@ -418,9 +418,9 @@ struct r600_common_context {
/* Render condition. */
struct r600_atom render_cond_atom;
struct pipe_query *current_render_cond;
unsigned current_render_cond_mode;
boolean current_render_cond_cond;
struct pipe_query *render_cond;
unsigned render_cond_mode;
boolean render_cond_invert;
bool render_cond_force_off; /* for u_blitter */
/* MSAA sample locations.

14
src/gallium/drivers/radeon/r600_query.c
View file

@ -307,7 +307,7 @@ static void r600_emit_query_predication(struct r600_common_context *ctx,
struct r600_atom *atom)
{
struct radeon_winsys_cs *cs = ctx->gfx.cs;
struct r600_query *query = (struct r600_query*)ctx->current_render_cond;
struct r600_query *query = (struct r600_query*)ctx->render_cond;
struct r600_query_buffer *qbuf;
uint32_t op;
bool flag_wait;
@ -315,8 +315,8 @@ static void r600_emit_query_predication(struct r600_common_context *ctx,
if (!query)
return;
flag_wait = ctx->current_render_cond_mode == PIPE_RENDER_COND_WAIT ||
ctx->current_render_cond_mode == PIPE_RENDER_COND_BY_REGION_WAIT;
flag_wait = ctx->render_cond_mode == PIPE_RENDER_COND_WAIT ||
ctx->render_cond_mode == PIPE_RENDER_COND_BY_REGION_WAIT;
switch (query->type) {
case PIPE_QUERY_OCCLUSION_COUNTER:
@ -335,7 +335,7 @@ static void r600_emit_query_predication(struct r600_common_context *ctx,
}
/* if true then invert, see GL_ARB_conditional_render_inverted */
if (ctx->current_render_cond_cond)
if (ctx->render_cond_invert)
op |= PREDICATION_DRAW_NOT_VISIBLE; /* Draw if not visable/overflow */
else
op |= PREDICATION_DRAW_VISIBLE; /* Draw if visable/overflow */
@ -831,9 +831,9 @@ static void r600_render_condition(struct pipe_context *ctx,
struct r600_query_buffer *qbuf;
struct r600_atom *atom = &rctx->render_cond_atom;
rctx->current_render_cond = query;
rctx->current_render_cond_cond = condition;
rctx->current_render_cond_mode = mode;
rctx->render_cond = query;
rctx->render_cond_invert = condition;
rctx->render_cond_mode = mode;
/* Compute the size of SET_PREDICATION packets. */
atom->num_dw = 0;

2
src/gallium/drivers/radeon/r600_texture.c
View file

@ -1324,7 +1324,7 @@ void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
{
int i;
if (rctx->current_render_cond)
if (rctx->render_cond)
return;
for (i = 0; i < fb->nr_cbufs; i++) {

2
src/gallium/drivers/radeonsi/si_state_draw.c
View file

@ -457,7 +457,7 @@ static void si_emit_draw_packets(struct si_context *sctx,
{
struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
unsigned sh_base_reg = sctx->shader_userdata.sh_base[PIPE_SHADER_VERTEX];
bool render_cond_bit = sctx->b.current_render_cond && !sctx->b.render_cond_force_off;
bool render_cond_bit = sctx->b.render_cond && !sctx->b.render_cond_force_off;
if (info->count_from_stream_output) {
struct r600_so_target *t =