diff --git a/src/nouveau/codegen/nv50_ir.h b/src/nouveau/codegen/nv50_ir.h
index f4c055f1131..235c9f44197 100644
--- a/src/nouveau/codegen/nv50_ir.h
+++ b/src/nouveau/codegen/nv50_ir.h
@@ -45,7 +45,6 @@ enum operation
    OP_UNION, // unify a new definition and several source values
    OP_SPLIT, // $r0d -> { $r0, $r1 } ($r0d and $r0/$r1 will be coalesced)
    OP_MERGE, // opposite of split, e.g. combine 2 32 bit into a 64 bit value
-   OP_CONSTRAINT, // copy values into consecutive registers
    OP_MOV, // simple copy, no modifiers allowed
    OP_LOAD,
    OP_STORE,
diff --git a/src/nouveau/codegen/nv50_ir_emit_gk110.cpp b/src/nouveau/codegen/nv50_ir_emit_gk110.cpp
index 4db0fdb95db..03f92aad3a9 100644
--- a/src/nouveau/codegen/nv50_ir_emit_gk110.cpp
+++ b/src/nouveau/codegen/nv50_ir_emit_gk110.cpp
@@ -2751,7 +2751,6 @@ CodeEmitterGK110::emitInstruction(Instruction *insn)
       break;
    case OP_PHI:
    case OP_UNION:
-   case OP_CONSTRAINT:
       ERROR("operation should have been eliminated");
       return false;
    case OP_SQRT:
diff --git a/src/nouveau/codegen/nv50_ir_emit_nv50.cpp b/src/nouveau/codegen/nv50_ir_emit_nv50.cpp
index a4f9af1b65f..2a33471704f 100644
--- a/src/nouveau/codegen/nv50_ir_emit_nv50.cpp
+++ b/src/nouveau/codegen/nv50_ir_emit_nv50.cpp
@@ -2125,7 +2125,6 @@ CodeEmitterNV50::emitInstruction(Instruction *insn)
       break;
    case OP_PHI:
    case OP_UNION:
-   case OP_CONSTRAINT:
       ERROR("operation should have been eliminated\n");
       return false;
    case OP_SQRT:
diff --git a/src/nouveau/codegen/nv50_ir_emit_nvc0.cpp b/src/nouveau/codegen/nv50_ir_emit_nvc0.cpp
index db34cde7da0..e9794828e81 100644
--- a/src/nouveau/codegen/nv50_ir_emit_nvc0.cpp
+++ b/src/nouveau/codegen/nv50_ir_emit_nvc0.cpp
@@ -2933,7 +2933,6 @@ CodeEmitterNVC0::emitInstruction(Instruction *insn)
       break;
    case OP_PHI:
    case OP_UNION:
-   case OP_CONSTRAINT:
       ERROR("operation should have been eliminated");
       return false;
    case OP_SQRT:
diff --git a/src/nouveau/codegen/nv50_ir_peephole.cpp b/src/nouveau/codegen/nv50_ir_peephole.cpp
index d06635439b5..55fe02c897f 100644
--- a/src/nouveau/codegen/nv50_ir_peephole.cpp
+++ b/src/nouveau/codegen/nv50_ir_peephole.cpp
@@ -33,7 +33,7 @@ namespace nv50_ir {
 bool
 Instruction::isNop() const
 {
-   if (op == OP_PHI || op == OP_SPLIT || op == OP_MERGE || op == OP_CONSTRAINT)
+   if (op == OP_PHI || op == OP_SPLIT || op == OP_MERGE)
       return true;
    if (terminator || join) // XXX: should terminator imply flow ?
       return false;
diff --git a/src/nouveau/codegen/nv50_ir_print.cpp b/src/nouveau/codegen/nv50_ir_print.cpp
index 09087e6c690..078e880ad2f 100644
--- a/src/nouveau/codegen/nv50_ir_print.cpp
+++ b/src/nouveau/codegen/nv50_ir_print.cpp
@@ -74,7 +74,6 @@ const char *operationStr[OP_LAST + 1] =
    "union",
    "split",
    "merge",
-   "consec",
    "mov",
    "ld",
    "st",
diff --git a/src/nouveau/codegen/nv50_ir_target.cpp b/src/nouveau/codegen/nv50_ir_target.cpp
index f203372b9e7..f3d971b2b2f 100644
--- a/src/nouveau/codegen/nv50_ir_target.cpp
+++ b/src/nouveau/codegen/nv50_ir_target.cpp
@@ -28,7 +28,7 @@ namespace nv50_ir {
 const uint8_t Target::operationSrcNr[] =
 {
    0, 0,                   // NOP, PHI
-   0, 0, 0, 0,             // UNION, SPLIT, MERGE, CONSTRAINT
+   0, 0, 0,                // UNION, SPLIT, MERGE
    1, 1, 2,                // MOV, LOAD, STORE
    2, 2, 2, 2, 2, 3, 3, 3, // ADD, SUB, MUL, DIV, MOD, MAD, FMA, SAD
    3, 3,                   // SHLADD, XMAD
@@ -65,10 +65,10 @@ const uint8_t Target::operationSrcNr[] =
 
 const OpClass Target::operationClass[] =
 {
-   // NOP; PHI; UNION, SPLIT, MERGE, CONSTRAINT
+   // NOP; PHI; UNION, SPLIT, MERGE
    OPCLASS_OTHER,
    OPCLASS_PSEUDO,
-   OPCLASS_PSEUDO, OPCLASS_PSEUDO, OPCLASS_PSEUDO, OPCLASS_PSEUDO,
+   OPCLASS_PSEUDO, OPCLASS_PSEUDO, OPCLASS_PSEUDO,
    // MOV; LOAD; STORE
    OPCLASS_MOVE,
    OPCLASS_LOAD,