From eadc134dd85477a3d038cb77adfeccffe88df295 Mon Sep 17 00:00:00 2001 From: Lionel Landwerlin Date: Tue, 7 Jun 2022 18:39:28 +0300 Subject: [PATCH] anv: fixup PIPE_CONTROL restriction on gfx8 We're missing a condition that is currently papered over by having ANV_PIPE_HDC_PIPELINE_FLUSH_BIT in the invalidate bits. v2: rework with simplication (Caio) Signed-off-by: Lionel Landwerlin Cc: mesa-stable Reviewed-by: Caio Oliveira Part-of: (cherry picked from commit 5e21f474288e2159c80a80fa20e7b473056df939) --- .pick_status.json | 2 +- src/intel/vulkan/genX_cmd_buffer.c | 18 ++++++++++++++++++ 2 files changed, 19 insertions(+), 1 deletion(-) diff --git a/.pick_status.json b/.pick_status.json index 3b1d13d92eb..c7cf44294b1 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -265,7 +265,7 @@ "description": "anv: fixup PIPE_CONTROL restriction on gfx8", "nominated": true, "nomination_type": 0, - "resolution": 0, + "resolution": 1, "main_sha": null, "because_sha": null }, diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index dc6c7ba8a25..c0b1ff76591 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -2109,6 +2109,24 @@ genX(emit_apply_pipe_flushes)(struct anv_batch *batch, #endif pipe.CommandStreamerStallEnable = bits & ANV_PIPE_CS_STALL_BIT; +#if GFX_VER == 8 + /* From Broadwell PRM, volume 2a: + * PIPE_CONTROL: Command Streamer Stall Enable: + * + * "This bit must be always set when PIPE_CONTROL command is + * programmed by GPGPU and MEDIA workloads, except for the cases + * when only Read Only Cache Invalidation bits are set (State + * Cache Invalidation Enable, Instruction cache Invalidation + * Enable, Texture Cache Invalidation Enable, Constant Cache + * Invalidation Enable). This is to WA FFDOP CG issue, this WA + * need not implemented when FF_DOP_CG is disabled." + * + * Since we do all the invalidation in the following PIPE_CONTROL, + * if we got here, we need a stall. + */ + pipe.CommandStreamerStallEnable |= current_pipeline == GPGPU; +#endif + pipe.StallAtPixelScoreboard = bits & ANV_PIPE_STALL_AT_SCOREBOARD_BIT; /* From Sandybridge PRM, volume 2, "1.7.3.1 Writing a Value to Memory":