fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-01-09 06:10:12 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 2

i965/gs: Add a flag allowing URB write messages to use a per-slot offset.

Browse source 
This will be used by geometry shaders to implement the EmitVertex()
function, since it requires writing data to a dynamically-determined
offset within the geometry shader's URB entry.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
This commit is contained in:
Paul Berry 2013-03-21 09:11:12 -07:00
parent a9e8c10bd7
commit eaa63cbbc2
2 changed files with 8 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

6
src/mesa/drivers/dri/i965/brw_eu.h
View file

@ -251,6 +251,12 @@ enum brw_urb_write_flags {
*/
BRW_URB_WRITE_COMPLETE = 0x8,
/**
* Indicates that an additional offset (which may be different for the two
* vec4 slots) is stored in the message header (gen == 7).
*/
BRW_URB_WRITE_PER_SLOT_OFFSET = 0x10,
/**
* Convenient combination of flags: end the thread while simultaneously
* marking the given URB entry as complete.

4
src/mesa/drivers/dri/i965/brw_eu_emit.c
View file

@ -531,8 +531,8 @@ static void brw_set_urb_message( struct brw_compile *p,
insn->bits3.urb_gen7.offset = offset;
assert(swizzle_control != BRW_URB_SWIZZLE_TRANSPOSE);
insn->bits3.urb_gen7.swizzle_control = swizzle_control;
/* per_slot_offset = 0 makes it ignore offsets in message header */
insn->bits3.urb_gen7.per_slot_offset = 0;
insn->bits3.urb_gen7.per_slot_offset =
flags & BRW_URB_WRITE_PER_SLOT_OFFSET ? 1 : 0;
insn->bits3.urb_gen7.complete = flags & BRW_URB_WRITE_COMPLETE ? 1 : 0;
} else if (brw->gen >= 5) {
insn->bits3.urb_gen5.opcode = 0; /* URB_WRITE */