From ea94cb95e4dc6da8ee458db276942be1f72afa44 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Tue, 27 Feb 2024 19:47:46 -0500 Subject: [PATCH] radeonsi/gfx10.3: add a GPU hang workaround for legacy tess+GS Fixes: a23802bcb9a - ac,radeonsi: start adding support for gfx10.3 Reviewed-by: Pierre-Eric Pelloux-Prayer Part-of: --- src/gallium/drivers/radeonsi/si_state.h | 2 +- src/gallium/drivers/radeonsi/si_state_shaders.cpp | 9 +++++++++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/radeonsi/si_state.h b/src/gallium/drivers/radeonsi/si_state.h index 3f7c8c64e4f..ae4e9b584aa 100644 --- a/src/gallium/drivers/radeonsi/si_state.h +++ b/src/gallium/drivers/radeonsi/si_state.h @@ -342,7 +342,7 @@ enum si_tracked_reg /* The slots below can be reused by other generations. */ SI_TRACKED_VGT_ESGS_RING_ITEMSIZE, /* GFX6-8 (GFX9+ can reuse this slot) */ - SI_TRACKED_VGT_REUSE_OFF, /* GFX6-8 (GFX9+ can reuse this slot) */ + SI_TRACKED_VGT_REUSE_OFF, /* GFX6-8,10.3 */ SI_TRACKED_IA_MULTI_VGT_PARAM, /* GFX6-8 (GFX9+ can reuse this slot) */ SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP, /* GFX9 - the slots above can be reused */ diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.cpp b/src/gallium/drivers/radeonsi/si_state_shaders.cpp index 758694a467e..4357d3034c6 100644 --- a/src/gallium/drivers/radeonsi/si_state_shaders.cpp +++ b/src/gallium/drivers/radeonsi/si_state_shaders.cpp @@ -4352,6 +4352,15 @@ static void si_emit_vgt_pipeline_state(struct si_context *sctx, unsigned index) radeon_begin(cs); radeon_opt_set_context_reg(sctx, R_028B54_VGT_SHADER_STAGES_EN, SI_TRACKED_VGT_SHADER_STAGES_EN, sctx->vgt_shader_stages_en); + if (sctx->gfx_level == GFX10_3) { + /* Legacy Tess+GS should disable reuse to prevent hangs on GFX10.3. */ + bool has_legacy_tess_gs = G_028B54_HS_EN(sctx->vgt_shader_stages_en) && + G_028B54_GS_EN(sctx->vgt_shader_stages_en) && + !G_028B54_PRIMGEN_EN(sctx->vgt_shader_stages_en); /* !NGG */ + + radeon_opt_set_context_reg(sctx, R_028AB4_VGT_REUSE_OFF, SI_TRACKED_VGT_REUSE_OFF, + S_028AB4_REUSE_OFF(has_legacy_tess_gs)); + } radeon_end_update_context_roll(sctx); if (sctx->gfx_level >= GFX10) {