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i965: Switch mapping modes for non-explicit-flush blit-temporary maps.

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On LLC, it should always be better to use a cached mapping than the GTT.
On non-LLC, it seems pretty silly to try to optimize read performance for
the INVALIDATE_RANGE_BIT case.  This will make the buffer_storage logic
easier.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Eric Anholt 2014-02-25 12:15:31 -08:00
parent ff1e850eec
commit ea93246c00
1 changed files with 3 additions and 3 deletions
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6
src/mesa/drivers/dri/i965/intel_buffer_objects.c
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@ -421,11 +421,11 @@ intel_bufferobj_map_range(struct gl_context * ctx,
"range map",
length + extra,
alignment);
if (!(access & GL_MAP_READ_BIT)) {
drm_intel_gem_bo_map_gtt(intel_obj->range_map_bo[index]);
} else {
if (brw->has_llc) {
drm_intel_bo_map(intel_obj->range_map_bo[index],
(access & GL_MAP_WRITE_BIT) != 0);
} else {
drm_intel_gem_bo_map_gtt(intel_obj->range_map_bo[index]);
}
obj->Mappings[index].Pointer =
intel_obj->range_map_bo[index]->virtual + extra;