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agx: quiesche assert with r1l preload

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fixes spilling in sample shaded frag shaders. this depends on the ABI
change in the last commit to be valid in the presence of subgroup ops.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31532>
This commit is contained in:
Alyssa Rosenzweig 2024-09-25 14:18:11 -04:00 • committed by Marge Bot
parent 7faca2220c
commit ea856ccec0
1 changed files with 9 additions and 0 deletions
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9
src/asahi/compiler/agx_register_allocate.c
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@ -1195,6 +1195,15 @@ agx_ra_assign_local(struct ra_ctx *rctx)
assert(I->dest[0].size == I->src[0].size);
assert(I->src[0].type == AGX_INDEX_REGISTER);
/* r1l specifically is a preloaded register. It is reserved during
* demand calculations to ensure we don't need live range shuffling of
* spilling temporaries. But we can still preload to it. So if it's
* reserved, just free it. It'll be fine.
*/
if (I->src[0].value == 2) {
BITSET_CLEAR(rctx->used_regs[RA_GPR], 2);
}
assign_regs(rctx, I->dest[0], I->src[0].value);
agx_set_dests(rctx, I);
continue;