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intel/brw: Temporarily disable result=float16 matrix configs
Even though the hardware does not naively support these configurations, there are many potential benefits to advertising them. These configurations can theoretically use half the memory bandwidth for loads and stores. For large matrices, that can be the limiting in performance. The current implementation, however, has a number of significant problems. The conversion from float16 to float32 is performed in the driver during conversion from NIR. As a result, many common usage patterns end up doing back-to-back conversions to and from float16 between matrix multiplications (when the result of one multiplication is used as the accumulator for the next). The float16 version of the matrix waste half the possible register space. Each float16 value sits alone in a dword. This is done so that the per-invocation slice of an 8x8 float16 result matrix and an 8x8 float32 result matrix will have the same number of elements. This makes it possible to do straightforward implementations of all the unary_op type conversions in NIR. It would be possible to perform N:M element type conversions in the backend using specialized NIR intrinsics. However, per #10961, this would be very, very painful. My hope is that, once a suitable resolution for that issue can be found, support for these configs can be restored. Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28834>
This commit is contained in:
Ian Romanick
parent
33dd38f9d5
commit
ea6e10c0b2
3 changed files with 23 additions and 91 deletions
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@ -4348,35 +4348,10 @@ fs_nir_emit_cs_intrinsic(nir_to_brw_state &ntb,
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dest = retype(dest, dest_type);
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fs_reg src0 = retype(get_nir_src(ntb, instr->src[0]), dest_type);
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const fs_reg dest_hf = dest;
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fs_builder bld16 = bld.exec_all().group(16, 0);
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fs_builder bldn = devinfo->ver >= 20 ? bld16 : bld.exec_all().group(8, 0);
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/* DG2 cannot have the destination or source 0 of DPAS be float16. It is
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* still advantageous to support these formats for memory and bandwidth
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* savings.
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*
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* The float16 source must be expanded to float32.
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*/
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if (devinfo->verx10 == 125 && dest_type == BRW_TYPE_HF &&
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!s.compiler->lower_dpas) {
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dest = bldn.vgrf(BRW_TYPE_F, rcount);
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if (src0.file != ARF) {
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const fs_reg src0_hf = src0;
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src0 = bldn.vgrf(BRW_TYPE_F, rcount);
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for (unsigned i = 0; i < 4; i++) {
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bld16.MOV(byte_offset(src0, REG_SIZE * i * 2),
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byte_offset(src0_hf, REG_SIZE * i));
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}
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} else {
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src0 = retype(src0, BRW_TYPE_F);
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}
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}
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bldn.DPAS(dest,
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src0,
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retype(get_nir_src(ntb, instr->src[2]), src_type),
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@ -4385,14 +4360,6 @@ fs_nir_emit_cs_intrinsic(nir_to_brw_state &ntb,
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rcount)
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->saturate = nir_intrinsic_saturate(instr);
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/* Compact the destination to float16 (from float32). */
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if (!dest.equals(dest_hf)) {
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for (unsigned i = 0; i < 4; i++) {
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bld16.MOV(byte_offset(dest_hf, REG_SIZE * i),
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byte_offset(dest, REG_SIZE * i * 2));
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}
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}
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cs_prog_data->uses_systolic = true;
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break;
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}
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@ -148,21 +148,14 @@ get_slice_type_from_desc(const struct lower_cmat_state *state,
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const unsigned element_bits = 32;
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const unsigned bits = glsl_base_type_get_bit_size(desc.element_type);
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unsigned packing_factor = MIN2(elements_per_invocation,
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element_bits / bits);
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/* Adjust the packing factor so that each row of the matrix fills and
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* entire GRF.
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*
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* The in-register layout of B matrices is different, so those are handled
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* more like column major (for row major matrices). See the file comment
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* for more details.
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/* Each invocation must have at least one dword of data, and that dword
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* must be tightly packed with values. No matter the matrix dimensions, a
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* matrix of uint8_t data must pack 4 values in each entry.
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*/
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const unsigned actual_cols = desc.use != GLSL_CMAT_USE_B ? desc.cols : desc.rows;
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while ((actual_cols / packing_factor) < 8) {
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assert(packing_factor > 1);
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packing_factor /= 2;
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}
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const unsigned packing_factor = element_bits / bits;
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assert(elements_per_invocation >= packing_factor);
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switch (desc.element_type) {
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case GLSL_TYPE_FLOAT:
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@ -172,12 +165,12 @@ get_slice_type_from_desc(const struct lower_cmat_state *state,
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case GLSL_TYPE_FLOAT16:
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case GLSL_TYPE_UINT8:
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case GLSL_TYPE_UINT16:
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base_type = glsl_get_base_type(glsl_uintN_t_type(packing_factor * bits));
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base_type = GLSL_TYPE_UINT;
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break;
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case GLSL_TYPE_INT:
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case GLSL_TYPE_INT8:
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case GLSL_TYPE_INT16:
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base_type = glsl_get_base_type(glsl_intN_t_type(packing_factor * bits));
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base_type = GLSL_TYPE_INT;
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break;
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default:
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unreachable("Invalid cooperative matrix element type.");
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@ -422,54 +415,30 @@ lower_cmat_unary_op(nir_builder *b, nir_intrinsic_instr *intrin,
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const nir_op op = nir_intrinsic_alu_op(intrin);
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/* There are three possible cases:
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*
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* 1. dst_packing_factor == src_packing_factor. This is the common case,
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* and handling it is straightforward.
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*
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* 2. dst_packing_factor > src_packing_factor. This occurs when converting a
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* float32_t matrix slice to a packed float16_t slice. Loop over the size
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* of the destination slice, but read multiple entries from the source
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* slice on each iteration.
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*
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* 3. dst_packing_factor < src_packing_factor. This occurs when converting a
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* packed int8_t matrix slice to an int32_t slice. Loop over the size of
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* the source slice, but write multiple entries to the destination slice
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* on each iteration.
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*
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* Handle all cases by iterating over the total (non-packed) number of
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* elements in the slice. When dst_packing_factor values have been
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* calculated, store them.
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/* With the combinations of formats exposed on all platforms, matrices with
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* the same dimensions will always have the same data size. The only real
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* type conversion possible is int32 <-> float32. As a result
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* dst_packing_factor == src_packing_factor.
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*/
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assert((dst_packing_factor * glsl_get_vector_elements(dst_slice->type)) ==
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(src_packing_factor * glsl_get_vector_elements(src_slice->type)));
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assert(dst_packing_factor == src_packing_factor);
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/* Stores at most dst_packing_factor partial results. */
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nir_def *v[4];
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assert(dst_packing_factor <= 4);
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for (unsigned i = 0; i < num_components * dst_packing_factor; i++) {
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const unsigned dst_chan_index = i % dst_packing_factor;
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const unsigned src_chan_index = i % src_packing_factor;
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const unsigned dst_index = i / dst_packing_factor;
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const unsigned src_index = i / src_packing_factor;
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for (unsigned i = 0; i < num_components; i++) {
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nir_def *chan = nir_channel(b, nir_load_deref(b, src_slice), i);
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nir_def *src =
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nir_channel(b,
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nir_unpack_bits(b,
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nir_channel(b,
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nir_load_deref(b, src_slice),
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src_index),
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src_bits),
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src_chan_index);
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for (unsigned j = 0; j < dst_packing_factor; j++) {
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nir_def *src =
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nir_channel(b, nir_unpack_bits(b, chan, src_bits), j);
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v[dst_chan_index] = nir_build_alu1(b, op, src);
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if (dst_chan_index == (dst_packing_factor - 1)) {
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results[dst_index] =
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nir_pack_bits(b, nir_vec(b, v, dst_packing_factor),
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dst_packing_factor * dst_bits);
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v[j] = nir_build_alu1(b, op, src);
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}
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results[i] =
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nir_pack_bits(b, nir_vec(b, v, dst_packing_factor),
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dst_packing_factor * dst_bits);
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}
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nir_store_deref(b, dst_slice, nir_vec(b, results, num_components),
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@ -620,7 +620,6 @@ static const struct intel_device_info intel_device_info_chv = {
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.has_sample_with_hiz = true, \
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.has_illegal_ccs_values = true, \
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.cooperative_matrix_configurations = { \
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{ INTEL_CMAT_SCOPE_SUBGROUP, 8, 8, 16, INTEL_CMAT_FLOAT16, INTEL_CMAT_FLOAT16, INTEL_CMAT_FLOAT16, INTEL_CMAT_FLOAT16 }, \
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{ INTEL_CMAT_SCOPE_SUBGROUP, 8, 8, 16, INTEL_CMAT_FLOAT16, INTEL_CMAT_FLOAT16, INTEL_CMAT_FLOAT32, INTEL_CMAT_FLOAT32 }, \
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{ INTEL_CMAT_SCOPE_SUBGROUP, 8, 8, 32, INTEL_CMAT_SINT8, INTEL_CMAT_SINT8, INTEL_CMAT_SINT32, INTEL_CMAT_SINT32 }, \
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{ INTEL_CMAT_SCOPE_SUBGROUP, 8, 8, 32, INTEL_CMAT_UINT8, INTEL_CMAT_UINT8, INTEL_CMAT_UINT32, INTEL_CMAT_UINT32 }, \
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@ -852,7 +851,6 @@ static const struct intel_device_info intel_device_info_cfl_gt3 = {
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.num_subslices = _subslices, \
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.max_eus_per_subslice = 8, \
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.cooperative_matrix_configurations = { \
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{ INTEL_CMAT_SCOPE_SUBGROUP, 8, 8, 16, INTEL_CMAT_FLOAT16, INTEL_CMAT_FLOAT16, INTEL_CMAT_FLOAT16, INTEL_CMAT_FLOAT16 }, \
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{ INTEL_CMAT_SCOPE_SUBGROUP, 8, 8, 16, INTEL_CMAT_FLOAT16, INTEL_CMAT_FLOAT16, INTEL_CMAT_FLOAT32, INTEL_CMAT_FLOAT32 }, \
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{ INTEL_CMAT_SCOPE_SUBGROUP, 8, 8, 32, INTEL_CMAT_SINT8, INTEL_CMAT_SINT8, INTEL_CMAT_SINT32, INTEL_CMAT_SINT32 }, \
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{ INTEL_CMAT_SCOPE_SUBGROUP, 8, 8, 32, INTEL_CMAT_UINT8, INTEL_CMAT_UINT8, INTEL_CMAT_UINT32, INTEL_CMAT_UINT32 }, \
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@ -985,7 +983,6 @@ static const struct intel_device_info intel_device_info_ehl_2x4 = {
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.writecombining = PAT_ENTRY(1, WC, NONE), \
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}, \
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.cooperative_matrix_configurations = { \
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{ INTEL_CMAT_SCOPE_SUBGROUP, 8, 8, 16, INTEL_CMAT_FLOAT16, INTEL_CMAT_FLOAT16, INTEL_CMAT_FLOAT16, INTEL_CMAT_FLOAT16 }, \
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{ INTEL_CMAT_SCOPE_SUBGROUP, 8, 8, 16, INTEL_CMAT_FLOAT16, INTEL_CMAT_FLOAT16, INTEL_CMAT_FLOAT32, INTEL_CMAT_FLOAT32 }, \
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{ INTEL_CMAT_SCOPE_SUBGROUP, 8, 8, 32, INTEL_CMAT_SINT8, INTEL_CMAT_SINT8, INTEL_CMAT_SINT32, INTEL_CMAT_SINT32 }, \
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{ INTEL_CMAT_SCOPE_SUBGROUP, 8, 8, 32, INTEL_CMAT_UINT8, INTEL_CMAT_UINT8, INTEL_CMAT_UINT32, INTEL_CMAT_UINT32 }, \
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@ -1117,7 +1114,6 @@ static const struct intel_device_info intel_device_info_sg1 = {
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.has_aux_map = false, \
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.simulator_id = 29, \
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.cooperative_matrix_configurations = { \
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{ INTEL_CMAT_SCOPE_SUBGROUP, 8, 8, 16, INTEL_CMAT_FLOAT16, INTEL_CMAT_FLOAT16, INTEL_CMAT_FLOAT16, INTEL_CMAT_FLOAT16 }, \
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{ INTEL_CMAT_SCOPE_SUBGROUP, 8, 8, 16, INTEL_CMAT_FLOAT16, INTEL_CMAT_FLOAT16, INTEL_CMAT_FLOAT32, INTEL_CMAT_FLOAT32 }, \
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{ INTEL_CMAT_SCOPE_SUBGROUP, 8, 8, 32, INTEL_CMAT_SINT8, INTEL_CMAT_SINT8, INTEL_CMAT_SINT32, INTEL_CMAT_SINT32 }, \
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{ INTEL_CMAT_SCOPE_SUBGROUP, 8, 8, 32, INTEL_CMAT_UINT8, INTEL_CMAT_UINT8, INTEL_CMAT_UINT32, INTEL_CMAT_UINT32 }, \
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