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radv: make sure to emit cache flushes before starting a query

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If the query pool has been previously resetted using the compute
shader path.

Fixes: a41e2e9cf5 ("radv: allow to use a compute shader for resetting the query pool")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105292
Cc: "18.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit c956d0f406)
This commit is contained in:
Samuel Pitoiset 2018-02-28 21:47:11 +01:00 • committed by Emil Velikov
parent 3a9454f9d4
commit ea43ba4e93
3 changed files with 33 additions and 7 deletions
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7
src/amd/vulkan/radv_cmd_buffer.c
View file

@ -2348,6 +2348,13 @@ VkResult radv_BeginCommandBuffer(
cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
/* Force cache flushes before starting a new query in case the
* corresponding pool has been resetted from a different command
* buffer. This is because we have to flush caches between reset and
* begin if the compute shader path has been used.
*/
cmd_buffer->pending_reset_query = true;
return result;
}

5
src/amd/vulkan/radv_private.h
View file

@ -987,6 +987,11 @@ struct radv_cmd_buffer {
uint32_t gfx9_fence_offset;
struct radeon_winsys_bo *gfx9_fence_bo;
uint32_t gfx9_fence_idx;
/**
* Whether a query pool has been resetted and we have to flush caches.
*/
bool pending_reset_query;
};
struct radv_image;

28
src/amd/vulkan/radv_query.c
View file

@ -1058,17 +1058,23 @@ void radv_CmdResetQueryPool(
{
RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
RADV_FROM_HANDLE(radv_query_pool, pool, queryPool);
struct radv_cmd_state *state = &cmd_buffer->state;
uint32_t flush_bits = 0;
state->flush_bits |= radv_fill_buffer(cmd_buffer, pool->bo,
firstQuery * pool->stride,
queryCount * pool->stride, 0);
flush_bits |= radv_fill_buffer(cmd_buffer, pool->bo,
firstQuery * pool->stride,
queryCount * pool->stride, 0);
if (pool->type == VK_QUERY_TYPE_TIMESTAMP ||
pool->type == VK_QUERY_TYPE_PIPELINE_STATISTICS) {
state->flush_bits |= radv_fill_buffer(cmd_buffer, pool->bo,
pool->availability_offset + firstQuery * 4,
queryCount * 4, 0);
flush_bits |= radv_fill_buffer(cmd_buffer, pool->bo,
pool->availability_offset + firstQuery * 4,
queryCount * 4, 0);
}
if (flush_bits) {
/* Only need to flush caches for the compute shader path. */
cmd_buffer->pending_reset_query = true;
cmd_buffer->state.flush_bits |= flush_bits;
}
}
@ -1086,6 +1092,14 @@ void radv_CmdBeginQuery(
radv_cs_add_buffer(cmd_buffer->device->ws, cs, pool->bo, 8);
if (cmd_buffer->pending_reset_query) {
/* Make sure to flush caches if the query pool has been
* previously resetted using the compute shader path.
*/
si_emit_cache_flush(cmd_buffer);
cmd_buffer->pending_reset_query = false;
}
switch (pool->type) {
case VK_QUERY_TYPE_OCCLUSION:
radeon_check_space(cmd_buffer->device->ws, cs, 7);