From ea3bfcf29ffdb21d1df0a6b3970fbea8fa33c2ac Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Mon, 25 Aug 2025 09:50:38 +0200 Subject: [PATCH] radv: pre-compute color blend enable Signed-off-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/radv_cmd_buffer.c | 19 ++++++++++--------- src/amd/vulkan/radv_pipeline_graphics.c | 2 +- src/amd/vulkan/radv_pipeline_graphics.h | 1 + 3 files changed, 12 insertions(+), 10 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 2ad4d83de7e..0fd86d9ebb1 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -684,11 +684,9 @@ radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer, const struct radv_dy } if (copy_mask & RADV_DYNAMIC_COLOR_BLEND_ENABLE) { - for (uint32_t i = 0; i < MAX_RTS; i++) { - if (dest->vk.cb.attachments[i].blend_enable != src->vk.cb.attachments[i].blend_enable) { - dest->vk.cb.attachments[i].blend_enable = src->vk.cb.attachments[i].blend_enable; - dest_mask |= RADV_DYNAMIC_COLOR_BLEND_ENABLE; - } + if (dest->color_blend_enable != src->color_blend_enable) { + dest->color_blend_enable = src->color_blend_enable; + dest_mask |= RADV_DYNAMIC_COLOR_BLEND_ENABLE; } } @@ -6046,7 +6044,6 @@ lookup_ps_epilog(struct radv_cmd_buffer *cmd_buffer) const uint32_t dst_blend = G_028780_COLOR_DESTBLEND(cb_blend_control); state.color_attachment_formats[i] = render->color_att[i].format; - state.color_blend_enable |= d->vk.cb.attachments[i].blend_enable << i; if (src_blend == V_028780_BLEND_SRC_ALPHA || src_blend == V_028780_BLEND_ONE_MINUS_SRC_ALPHA || src_blend == V_028780_BLEND_SRC_ALPHA_SATURATE || dst_blend == V_028780_BLEND_SRC_ALPHA || @@ -6059,6 +6056,7 @@ lookup_ps_epilog(struct radv_cmd_buffer *cmd_buffer) } state.color_write_mask = d->color_write_mask; + state.color_blend_enable = d->color_blend_enable; state.mrt0_is_dual_src = d->mrt0_is_dual_src; if (d->vk.ms.alpha_to_coverage_enable) { @@ -9045,15 +9043,18 @@ radv_CmdSetColorBlendEnableEXT(VkCommandBuffer commandBuffer, uint32_t firstAtta { VK_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer); struct radv_cmd_state *state = &cmd_buffer->state; + uint32_t color_blend_enable = state->dynamic.color_blend_enable; assert(firstAttachment + attachmentCount <= MAX_RTS); for (uint32_t i = 0; i < attachmentCount; i++) { uint32_t idx = firstAttachment + i; - state->dynamic.vk.cb.attachments[idx].blend_enable = pColorBlendEnables[i]; + color_blend_enable &= ~BITFIELD_RANGE(idx, 1); + color_blend_enable |= pColorBlendEnables[i] << idx; } + state->dynamic.color_blend_enable = color_blend_enable; state->dirty_dynamic |= RADV_DYNAMIC_COLOR_BLEND_ENABLE; } @@ -11251,7 +11252,7 @@ radv_emit_db_shader_control(struct radv_cmd_buffer *cmd_buffer) } } else if (gpu_info->has_export_conflict_bug && rasterization_samples == 1) { for (uint32_t i = 0; i < MAX_RTS; i++) { - if (((d->color_write_mask >> (4 * i)) & 0xfu) && d->vk.cb.attachments[i].blend_enable) { + if (((d->color_write_mask >> (4 * i)) & 0xfu) && ((d->color_blend_enable >> i) & 0x1u)) { db_shader_control |= S_02880C_OVERRIDE_INTRINSIC_RATE_ENABLE(1) | S_02880C_OVERRIDE_INTRINSIC_RATE(2); break; } @@ -11588,7 +11589,7 @@ radv_emit_cb_render_state(struct radv_cmd_buffer *cmd_buffer) continue; } - if (!d->vk.cb.attachments[i].blend_enable) { + if (!((d->color_blend_enable >> i) & 0x1u)) { sx_mrt_blend_opt[i] |= S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED); continue; diff --git a/src/amd/vulkan/radv_pipeline_graphics.c b/src/amd/vulkan/radv_pipeline_graphics.c index c503159a3fd..b0f6d3798a1 100644 --- a/src/amd/vulkan/radv_pipeline_graphics.c +++ b/src/amd/vulkan/radv_pipeline_graphics.c @@ -1033,7 +1033,7 @@ radv_pipeline_init_dynamic_state(const struct radv_device *device, struct radv_g if (states & RADV_DYNAMIC_COLOR_BLEND_ENABLE) { for (unsigned i = 0; i < state->cb->attachment_count; i++) { - dynamic->vk.cb.attachments[i].blend_enable = state->cb->attachments[i].blend_enable; + dynamic->color_blend_enable |= state->cb->attachments[i].blend_enable << i; } } diff --git a/src/amd/vulkan/radv_pipeline_graphics.h b/src/amd/vulkan/radv_pipeline_graphics.h index 39b794a3341..2c671c8edb6 100644 --- a/src/amd/vulkan/radv_pipeline_graphics.h +++ b/src/amd/vulkan/radv_pipeline_graphics.h @@ -64,6 +64,7 @@ struct radv_dynamic_state { uint32_t color_write_enable; uint32_t color_write_mask; + uint8_t color_blend_enable; bool mrt0_is_dual_src;