mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
synced 2025-12-25 17:20:10 +01:00
nak: Move some calc_instr_deps items to a new file
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32311>
This commit is contained in:
Faith Ekstrand
Marge Bot
parent
0ba5d99a61
commit
e9ff848095
3 changed files with 261 additions and 254 deletions
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@ -3,134 +3,12 @@
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use crate::api::{GetDebugFlags, DEBUG};
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use crate::ir::*;
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use crate::sched_common::*;
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use std::cmp::max;
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use std::collections::{HashMap, HashSet};
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use std::ops::{Index, IndexMut, Range};
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use std::slice;
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struct RegTracker<T> {
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reg: [T; 255],
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ureg: [T; 63],
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pred: [T; 7],
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upred: [T; 7],
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carry: [T; 1],
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}
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fn new_array_with<T, const N: usize>(f: &impl Fn() -> T) -> [T; N] {
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let mut v = Vec::new();
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for _ in 0..N {
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v.push(f());
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}
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v.try_into()
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.unwrap_or_else(|_| panic!("Array size mismatch"))
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}
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impl<T> RegTracker<T> {
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pub fn new_with(f: &impl Fn() -> T) -> Self {
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Self {
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reg: new_array_with(f),
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ureg: new_array_with(f),
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pred: new_array_with(f),
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upred: new_array_with(f),
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carry: new_array_with(f),
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}
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}
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pub fn for_each_instr_pred_mut(
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&mut self,
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instr: &Instr,
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mut f: impl FnMut(&mut T),
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) {
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if let PredRef::Reg(reg) = &instr.pred.pred_ref {
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for i in &mut self[*reg] {
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f(i);
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}
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}
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}
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pub fn for_each_instr_src_mut(
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&mut self,
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instr: &Instr,
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mut f: impl FnMut(usize, &mut T),
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) {
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for (i, src) in instr.srcs().iter().enumerate() {
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match &src.src_ref {
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SrcRef::Reg(reg) => {
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for t in &mut self[*reg] {
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f(i, t);
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}
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}
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SrcRef::CBuf(CBufRef {
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buf: CBuf::BindlessUGPR(reg),
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..
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}) => {
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for t in &mut self[*reg] {
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f(i, t);
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}
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}
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_ => (),
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}
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}
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}
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pub fn for_each_instr_dst_mut(
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&mut self,
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instr: &Instr,
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mut f: impl FnMut(usize, &mut T),
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) {
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for (i, dst) in instr.dsts().iter().enumerate() {
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if let Dst::Reg(reg) = dst {
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for t in &mut self[*reg] {
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f(i, t);
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}
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}
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}
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}
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}
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impl<T> Index<RegRef> for RegTracker<T> {
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type Output = [T];
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fn index(&self, reg: RegRef) -> &[T] {
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let range = reg.idx_range();
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let range = Range {
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start: usize::try_from(range.start).unwrap(),
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end: usize::try_from(range.end).unwrap(),
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};
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match reg.file() {
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RegFile::GPR => &self.reg[range],
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RegFile::UGPR => &self.ureg[range],
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RegFile::Pred => &self.pred[range],
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RegFile::UPred => &self.upred[range],
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RegFile::Carry => &self.carry[range],
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RegFile::Bar => &[], // Barriers have a HW scoreboard
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RegFile::Mem => panic!("Not a register"),
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}
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}
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}
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impl<T> IndexMut<RegRef> for RegTracker<T> {
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fn index_mut(&mut self, reg: RegRef) -> &mut [T] {
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let range = reg.idx_range();
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let range = Range {
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start: usize::try_from(range.start).unwrap(),
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end: usize::try_from(range.end).unwrap(),
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};
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match reg.file() {
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RegFile::GPR => &mut self.reg[range],
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RegFile::UGPR => &mut self.ureg[range],
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RegFile::Pred => &mut self.pred[range],
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RegFile::UPred => &mut self.upred[range],
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RegFile::Carry => &mut self.carry[range],
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RegFile::Bar => &mut [], // Barriers have a HW scoreboard
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RegFile::Mem => panic!("Not a register"),
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}
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}
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}
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#[derive(Clone)]
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enum RegUse<T: Clone> {
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None,
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@ -463,137 +341,6 @@ fn assign_barriers(f: &mut Function, sm: &dyn ShaderModel) {
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}
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}
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fn exec_latency(sm: u8, op: &Op) -> u32 {
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if sm >= 70 {
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match op {
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Op::Bar(_) | Op::MemBar(_) => {
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if sm >= 80 {
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6
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} else {
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5
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}
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}
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Op::CCtl(_op) => {
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// CCTL.C needs 8, CCTL.I needs 11
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11
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}
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// Op::DepBar(_) => 4,
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_ => 1, // TODO: co-issue
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}
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} else {
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match op {
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Op::CCtl(_)
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| Op::MemBar(_)
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| Op::Bra(_)
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| Op::SSy(_)
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| Op::Sync(_)
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| Op::Brk(_)
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| Op::PBk(_)
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| Op::Cont(_)
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| Op::PCnt(_)
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| Op::Exit(_)
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| Op::Bar(_)
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| Op::Kill(_)
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| Op::OutFinal(_) => 13,
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_ => 1,
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}
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}
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}
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fn instr_latency(sm: u8, op: &Op, dst_idx: usize) -> u32 {
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let file = match op.dsts_as_slice()[dst_idx] {
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Dst::None => return 0,
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Dst::SSA(vec) => vec.file().unwrap(),
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Dst::Reg(reg) => reg.file(),
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};
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let (gpr_latency, pred_latency) = if sm < 80 {
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match op {
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// Double-precision float ALU
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Op::DAdd(_)
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| Op::DFma(_)
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| Op::DMnMx(_)
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| Op::DMul(_)
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| Op::DSetP(_)
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// Half-precision float ALU
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| Op::HAdd2(_)
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| Op::HFma2(_)
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| Op::HMul2(_)
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| Op::HSet2(_)
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| Op::HSetP2(_)
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| Op::HMnMx2(_) => if sm == 70 {
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// Volta is even slower
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(13, 15)
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} else {
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(13, 14)
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}
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_ => (6, 13)
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}
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} else {
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(6, 13)
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};
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// This is BS and we know it
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match file {
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RegFile::GPR => gpr_latency,
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RegFile::UGPR => 12,
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RegFile::Pred => pred_latency,
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RegFile::UPred => 11,
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RegFile::Bar => 0, // Barriers have a HW scoreboard
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RegFile::Carry => 6,
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RegFile::Mem => panic!("Not a register"),
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}
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}
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/// Read-after-write latency
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fn raw_latency(
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sm: u8,
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write: &Op,
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dst_idx: usize,
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_read: &Op,
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_src_idx: usize,
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) -> u32 {
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instr_latency(sm, write, dst_idx)
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}
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/// Write-after-read latency
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fn war_latency(
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_sm: u8,
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_read: &Op,
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_src_idx: usize,
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_write: &Op,
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_dst_idx: usize,
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) -> u32 {
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// We assume the source gets read in the first 4 cycles. We don't know how
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// quickly the write will happen. This is all a guess.
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4
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}
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/// Write-after-write latency
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fn waw_latency(
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sm: u8,
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a: &Op,
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a_dst_idx: usize,
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_b: &Op,
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_b_dst_idx: usize,
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) -> u32 {
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// We know our latencies are wrong so assume the wrote could happen anywhere
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// between 0 and instr_latency(a) cycles
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instr_latency(sm, a, a_dst_idx)
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}
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/// Predicate read-after-write latency
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fn paw_latency(sm: u8, write: &Op, _dst_idx: usize) -> u32 {
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if sm == 70 {
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match write {
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Op::DSetP(_) | Op::HSetP2(_) => 15,
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_ => 13,
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}
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} else {
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13
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}
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}
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fn calc_delays(f: &mut Function, sm: &dyn ShaderModel) {
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for b in f.blocks.iter_mut().rev() {
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let mut cycle = 0_u32;
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@ -23,6 +23,7 @@ mod opt_prmt;
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mod opt_uniform_instrs;
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mod qmd;
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mod repair_ssa;
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mod sched_common;
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mod sm50;
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mod sm70;
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mod sph;
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259
src/nouveau/compiler/nak/sched_common.rs
Normal file
259
src/nouveau/compiler/nak/sched_common.rs
Normal file
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@ -0,0 +1,259 @@
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// Copyright © 2022 Collabora, Ltd.
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// SPDX-License-Identifier: MIT
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use crate::ir::*;
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use std::ops::{Index, IndexMut, Range};
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pub fn exec_latency(sm: u8, op: &Op) -> u32 {
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if sm >= 70 {
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match op {
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Op::Bar(_) | Op::MemBar(_) => {
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if sm >= 80 {
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6
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} else {
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5
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}
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}
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Op::CCtl(_op) => {
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// CCTL.C needs 8, CCTL.I needs 11
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11
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}
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// Op::DepBar(_) => 4,
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_ => 1, // TODO: co-issue
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}
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} else {
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match op {
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Op::CCtl(_)
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| Op::MemBar(_)
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| Op::Bra(_)
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| Op::SSy(_)
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| Op::Sync(_)
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| Op::Brk(_)
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| Op::PBk(_)
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| Op::Cont(_)
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| Op::PCnt(_)
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| Op::Exit(_)
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| Op::Bar(_)
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| Op::Kill(_)
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| Op::OutFinal(_) => 13,
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_ => 1,
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}
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}
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}
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pub fn instr_latency(sm: u8, op: &Op, dst_idx: usize) -> u32 {
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let file = match op.dsts_as_slice()[dst_idx] {
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Dst::None => return 0,
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Dst::SSA(vec) => vec.file().unwrap(),
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Dst::Reg(reg) => reg.file(),
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};
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let (gpr_latency, pred_latency) = if sm < 80 {
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match op {
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// Double-precision float ALU
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Op::DAdd(_)
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| Op::DFma(_)
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| Op::DMnMx(_)
|
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| Op::DMul(_)
|
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| Op::DSetP(_)
|
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// Half-precision float ALU
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| Op::HAdd2(_)
|
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| Op::HFma2(_)
|
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| Op::HMul2(_)
|
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| Op::HSet2(_)
|
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| Op::HSetP2(_)
|
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| Op::HMnMx2(_) => if sm == 70 {
|
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// Volta is even slower
|
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(13, 15)
|
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} else {
|
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(13, 14)
|
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}
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_ => (6, 13)
|
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}
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} else {
|
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(6, 13)
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};
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|
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// This is BS and we know it
|
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match file {
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RegFile::GPR => gpr_latency,
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RegFile::UGPR => 12,
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RegFile::Pred => pred_latency,
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RegFile::UPred => 11,
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RegFile::Bar => 0, // Barriers have a HW scoreboard
|
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RegFile::Carry => 6,
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RegFile::Mem => panic!("Not a register"),
|
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}
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}
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|
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/// Read-after-write latency
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pub fn raw_latency(
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sm: u8,
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write: &Op,
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dst_idx: usize,
|
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_read: &Op,
|
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_src_idx: usize,
|
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) -> u32 {
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instr_latency(sm, write, dst_idx)
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}
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|
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/// Write-after-read latency
|
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pub fn war_latency(
|
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_sm: u8,
|
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_read: &Op,
|
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_src_idx: usize,
|
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_write: &Op,
|
||||
_dst_idx: usize,
|
||||
) -> u32 {
|
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// We assume the source gets read in the first 4 cycles. We don't know how
|
||||
// quickly the write will happen. This is all a guess.
|
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4
|
||||
}
|
||||
|
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/// Write-after-write latency
|
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pub fn waw_latency(
|
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sm: u8,
|
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a: &Op,
|
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a_dst_idx: usize,
|
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_b: &Op,
|
||||
_b_dst_idx: usize,
|
||||
) -> u32 {
|
||||
// We know our latencies are wrong so assume the wrote could happen anywhere
|
||||
// between 0 and instr_latency(a) cycles
|
||||
instr_latency(sm, a, a_dst_idx)
|
||||
}
|
||||
|
||||
/// Predicate read-after-write latency
|
||||
pub fn paw_latency(sm: u8, write: &Op, _dst_idx: usize) -> u32 {
|
||||
if sm == 70 {
|
||||
match write {
|
||||
Op::DSetP(_) | Op::HSetP2(_) => 15,
|
||||
_ => 13,
|
||||
}
|
||||
} else {
|
||||
13
|
||||
}
|
||||
}
|
||||
|
||||
pub struct RegTracker<T> {
|
||||
reg: [T; 255],
|
||||
ureg: [T; 63],
|
||||
pred: [T; 7],
|
||||
upred: [T; 7],
|
||||
carry: [T; 1],
|
||||
}
|
||||
|
||||
fn new_array_with<T, const N: usize>(f: &impl Fn() -> T) -> [T; N] {
|
||||
let mut v = Vec::new();
|
||||
for _ in 0..N {
|
||||
v.push(f());
|
||||
}
|
||||
v.try_into()
|
||||
.unwrap_or_else(|_| panic!("Array size mismatch"))
|
||||
}
|
||||
|
||||
impl<T> RegTracker<T> {
|
||||
pub fn new_with(f: &impl Fn() -> T) -> Self {
|
||||
Self {
|
||||
reg: new_array_with(f),
|
||||
ureg: new_array_with(f),
|
||||
pred: new_array_with(f),
|
||||
upred: new_array_with(f),
|
||||
carry: new_array_with(f),
|
||||
}
|
||||
}
|
||||
|
||||
pub fn for_each_instr_pred_mut(
|
||||
&mut self,
|
||||
instr: &Instr,
|
||||
mut f: impl FnMut(&mut T),
|
||||
) {
|
||||
if let PredRef::Reg(reg) = &instr.pred.pred_ref {
|
||||
for i in &mut self[*reg] {
|
||||
f(i);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pub fn for_each_instr_src_mut(
|
||||
&mut self,
|
||||
instr: &Instr,
|
||||
mut f: impl FnMut(usize, &mut T),
|
||||
) {
|
||||
for (i, src) in instr.srcs().iter().enumerate() {
|
||||
match &src.src_ref {
|
||||
SrcRef::Reg(reg) => {
|
||||
for t in &mut self[*reg] {
|
||||
f(i, t);
|
||||
}
|
||||
}
|
||||
SrcRef::CBuf(CBufRef {
|
||||
buf: CBuf::BindlessUGPR(reg),
|
||||
..
|
||||
}) => {
|
||||
for t in &mut self[*reg] {
|
||||
f(i, t);
|
||||
}
|
||||
}
|
||||
_ => (),
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pub fn for_each_instr_dst_mut(
|
||||
&mut self,
|
||||
instr: &Instr,
|
||||
mut f: impl FnMut(usize, &mut T),
|
||||
) {
|
||||
for (i, dst) in instr.dsts().iter().enumerate() {
|
||||
if let Dst::Reg(reg) = dst {
|
||||
for t in &mut self[*reg] {
|
||||
f(i, t);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl<T> Index<RegRef> for RegTracker<T> {
|
||||
type Output = [T];
|
||||
|
||||
fn index(&self, reg: RegRef) -> &[T] {
|
||||
let range = reg.idx_range();
|
||||
let range = Range {
|
||||
start: usize::try_from(range.start).unwrap(),
|
||||
end: usize::try_from(range.end).unwrap(),
|
||||
};
|
||||
|
||||
match reg.file() {
|
||||
RegFile::GPR => &self.reg[range],
|
||||
RegFile::UGPR => &self.ureg[range],
|
||||
RegFile::Pred => &self.pred[range],
|
||||
RegFile::UPred => &self.upred[range],
|
||||
RegFile::Carry => &self.carry[range],
|
||||
RegFile::Bar => &[], // Barriers have a HW scoreboard
|
||||
RegFile::Mem => panic!("Not a register"),
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl<T> IndexMut<RegRef> for RegTracker<T> {
|
||||
fn index_mut(&mut self, reg: RegRef) -> &mut [T] {
|
||||
let range = reg.idx_range();
|
||||
let range = Range {
|
||||
start: usize::try_from(range.start).unwrap(),
|
||||
end: usize::try_from(range.end).unwrap(),
|
||||
};
|
||||
|
||||
match reg.file() {
|
||||
RegFile::GPR => &mut self.reg[range],
|
||||
RegFile::UGPR => &mut self.ureg[range],
|
||||
RegFile::Pred => &mut self.pred[range],
|
||||
RegFile::UPred => &mut self.upred[range],
|
||||
RegFile::Carry => &mut self.carry[range],
|
||||
RegFile::Bar => &mut [], // Barriers have a HW scoreboard
|
||||
RegFile::Mem => panic!("Not a register"),
|
||||
}
|
||||
}
|
||||
}
|
||||
Loading…
Add table
Reference in a new issue