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gen7/pipeline: Re-arrange stencil parameters to match gen8

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This commit is contained in:
Jason Ekstrand 2015-11-17 19:10:31 -08:00
parent 9e39bdabad
commit e9d634f4ad
1 changed files with 10 additions and 11 deletions
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21
src/vulkan/gen7_pipeline.c
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@ -227,27 +227,26 @@ gen7_emit_ds_state(struct anv_pipeline *pipeline,
bool has_stencil = false; /* enable if subpass has stencil? */
struct GEN7_DEPTH_STENCIL_STATE state = {
.DepthTestEnable = info->depthTestEnable,
.DepthBufferWriteEnable = info->depthWriteEnable,
.DepthTestFunction = vk_to_gen_compare_op[info->depthCompareOp],
.DoubleSidedStencilEnable = true,
/* Is this what we need to do? */
.StencilBufferWriteEnable = has_stencil,
.StencilTestEnable = info->stencilTestEnable,
.StencilTestFunction = vk_to_gen_compare_op[info->front.stencilCompareOp],
.StencilFailOp = vk_to_gen_stencil_op[info->front.stencilFailOp],
.StencilPassDepthFailOp = vk_to_gen_stencil_op[info->front.stencilDepthFailOp],
.StencilPassDepthPassOp = vk_to_gen_stencil_op[info->front.stencilPassOp],
.StencilPassDepthFailOp = vk_to_gen_stencil_op[info->front.stencilDepthFailOp],
.StencilTestFunction = vk_to_gen_compare_op[info->front.stencilCompareOp],
.DoubleSidedStencilEnable = true,
.BackFaceStencilTestFunction = vk_to_gen_compare_op[info->back.stencilCompareOp],
.BackfaceStencilFailOp = vk_to_gen_stencil_op[info->back.stencilFailOp],
.BackfaceStencilPassDepthFailOp = vk_to_gen_stencil_op[info->back.stencilDepthFailOp],
.BackfaceStencilPassDepthPassOp = vk_to_gen_stencil_op[info->back.stencilPassOp],
.DepthTestEnable = info->depthTestEnable,
.DepthTestFunction = vk_to_gen_compare_op[info->depthCompareOp],
.DepthBufferWriteEnable = info->depthWriteEnable,
.BackfaceStencilPassDepthFailOp = vk_to_gen_stencil_op[info->back.stencilDepthFailOp],
.BackFaceStencilTestFunction = vk_to_gen_compare_op[info->back.stencilCompareOp],
};
GEN7_DEPTH_STENCIL_STATE_pack(NULL, &pipeline->gen7.depth_stencil_state, &state);
}