diff --git a/docs/gallium/screen.rst b/docs/gallium/screen.rst index a4475df2c24..06c4bbf4d10 100644 --- a/docs/gallium/screen.rst +++ b/docs/gallium/screen.rst @@ -552,10 +552,6 @@ The integer capabilities: * ``PIPE_CAP_COMPUTE_GRID_INFO_LAST_BLOCK``: Whether pipe_grid_info::last_block is implemented by the driver. See struct pipe_grid_info for more details. * ``PIPE_CAP_COMPUTE_SHADER_DERIVATIVE``: True if the driver supports derivatives (and texture lookups with implicit derivatives) in compute shaders. -* ``PIPE_CAP_TGSI_SKIP_SHRINK_IO_ARRAYS``: Whether the TGSI pass to shrink IO - arrays should be skipped and enforce keeping the declared array sizes instead. - A driver might rely on the input mapping that was defined with the original - GLSL code. * ``PIPE_CAP_IMAGE_LOAD_FORMATTED``: True if a format for image loads does not need to be specified in the shader IR * ``PIPE_CAP_IMAGE_STORE_FORMATTED``: True if a format for image stores does not need to be specified in the shader IR * ``PIPE_CAP_THROTTLE``: Whether or not gallium frontends should throttle pipe_context @@ -740,8 +736,6 @@ MOV OUT[0], CONST[0][3] # copy vector 3 of constbuf 0 * ``PIPE_SHADER_CAP_DFRACEXP_DLDEXP_SUPPORTED``: Whether DFRACEXP and DLDEXP are supported. * ``PIPE_SHADER_CAP_LDEXP_SUPPORTED``: Whether LDEXP is supported. -* ``PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED``: Whether FMA and DFMA (doubles only) - are supported. * ``PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE``: Whether the driver doesn't ignore tgsi_declaration_range::Last for shader inputs and outputs. * ``PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT``: This is the maximum number @@ -755,13 +749,6 @@ MOV OUT[0], CONST[0][3] # copy vector 3 of constbuf 0 * ``PIPE_SHADER_CAP_SUPPORTED_IRS``: Supported representations of the program. It should be a mask of ``pipe_shader_ir`` bits. * ``PIPE_SHADER_CAP_MAX_SHADER_IMAGES``: Maximum number of image units. -* ``PIPE_SHADER_CAP_LOWER_IF_THRESHOLD``: IF and ELSE branches with a lower - cost than this value should be lowered by gallium frontends for better - performance. This is a tunable for the GLSL compiler and the behavior is - specific to the compiler. -* ``PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS``: Whether the merge registers - TGSI pass is skipped. This might reduce code size and register pressure if - the underlying driver has a real backend compiler. * ``PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS``: If atomic counters are separate, how many HW counters are available for this stage. (0 uses SSBO atomics). * ``PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS``: If atomic counters are diff --git a/src/gallium/auxiliary/gallivm/lp_bld_limits.h b/src/gallium/auxiliary/gallivm/lp_bld_limits.h index 524d774ed65..b5034b24dce 100644 --- a/src/gallium/auxiliary/gallivm/lp_bld_limits.h +++ b/src/gallium/auxiliary/gallivm/lp_bld_limits.h @@ -155,9 +155,6 @@ gallivm_get_shader_param(enum pipe_shader_cap param) case PIPE_SHADER_CAP_DROUND_SUPPORTED: case PIPE_SHADER_CAP_DFRACEXP_DLDEXP_SUPPORTED: case PIPE_SHADER_CAP_LDEXP_SUPPORTED: - case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED: - case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD: - case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS: case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS: case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS: return 0; diff --git a/src/gallium/auxiliary/tgsi/tgsi_exec.h b/src/gallium/auxiliary/tgsi/tgsi_exec.h index 272e523c358..226385ae3a3 100644 --- a/src/gallium/auxiliary/tgsi/tgsi_exec.h +++ b/src/gallium/auxiliary/tgsi/tgsi_exec.h @@ -485,9 +485,6 @@ tgsi_exec_get_shader_param(enum pipe_shader_cap param) case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE: return 1; case PIPE_SHADER_CAP_DROUND_SUPPORTED: - case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED: - case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD: - case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS: case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS: case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS: return 0; diff --git a/src/gallium/auxiliary/util/u_screen.c b/src/gallium/auxiliary/util/u_screen.c index 52db3a840fc..b9a1ccb552e 100644 --- a/src/gallium/auxiliary/util/u_screen.c +++ b/src/gallium/auxiliary/util/u_screen.c @@ -361,7 +361,6 @@ u_pipe_screen_get_param_defaults(struct pipe_screen *pscreen, case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS: case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS: case PIPE_CAP_IMAGE_ATOMIC_FLOAT_ADD: - case PIPE_CAP_TGSI_SKIP_SHRINK_IO_ARRAYS: case PIPE_CAP_IMAGE_LOAD_FORMATTED: case PIPE_CAP_IMAGE_STORE_FORMATTED: case PIPE_CAP_PREFER_COMPUTE_FOR_MULTIMEDIA: diff --git a/src/gallium/drivers/asahi/agx_pipe.c b/src/gallium/drivers/asahi/agx_pipe.c index 996c61ae257..a77a01f8846 100644 --- a/src/gallium/drivers/asahi/agx_pipe.c +++ b/src/gallium/drivers/asahi/agx_pipe.c @@ -950,7 +950,6 @@ agx_get_shader_param(struct pipe_screen* pscreen, case PIPE_SHADER_CAP_DROUND_SUPPORTED: case PIPE_SHADER_CAP_DFRACEXP_DLDEXP_SUPPORTED: case PIPE_SHADER_CAP_LDEXP_SUPPORTED: - case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED: case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE: return 0; @@ -971,8 +970,6 @@ agx_get_shader_param(struct pipe_screen* pscreen, case PIPE_SHADER_CAP_MAX_SHADER_IMAGES: case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS: case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS: - case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS: - case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD: return 0; default: diff --git a/src/gallium/drivers/crocus/crocus_screen.c b/src/gallium/drivers/crocus/crocus_screen.c index 60942271a55..52a54a1e248 100644 --- a/src/gallium/drivers/crocus/crocus_screen.c +++ b/src/gallium/drivers/crocus/crocus_screen.c @@ -523,10 +523,7 @@ crocus_get_shader_param(struct pipe_screen *pscreen, case PIPE_SHADER_CAP_DROUND_SUPPORTED: case PIPE_SHADER_CAP_LDEXP_SUPPORTED: return 1; - case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD: - case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS: case PIPE_SHADER_CAP_DFRACEXP_DLDEXP_SUPPORTED: - case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED: case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE: case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED: case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT: diff --git a/src/gallium/drivers/d3d12/d3d12_screen.cpp b/src/gallium/drivers/d3d12/d3d12_screen.cpp index a20a48f2704..093697e6bef 100644 --- a/src/gallium/drivers/d3d12/d3d12_screen.cpp +++ b/src/gallium/drivers/d3d12/d3d12_screen.cpp @@ -461,7 +461,6 @@ d3d12_get_shader_param(struct pipe_screen *pscreen, case PIPE_SHADER_CAP_DROUND_SUPPORTED: case PIPE_SHADER_CAP_DFRACEXP_DLDEXP_SUPPORTED: - case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED: return 0; /* not implemented */ case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE: @@ -487,10 +486,6 @@ d3d12_get_shader_param(struct pipe_screen *pscreen, screen->opts.ResourceBindingTier >= D3D12_RESOURCE_BINDING_TIER_3) ? PIPE_MAX_SHADER_IMAGES : D3D12_PS_CS_UAV_REGISTER_COUNT; - case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD: - case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS: - return 0; /* unsure */ - case PIPE_SHADER_CAP_LDEXP_SUPPORTED: case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS: case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS: diff --git a/src/gallium/drivers/etnaviv/etnaviv_screen.c b/src/gallium/drivers/etnaviv/etnaviv_screen.c index b82063f4858..684370b5132 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_screen.c +++ b/src/gallium/drivers/etnaviv/etnaviv_screen.c @@ -410,7 +410,6 @@ etna_screen_get_shader_param(struct pipe_screen *pscreen, case PIPE_SHADER_CAP_DROUND_SUPPORTED: case PIPE_SHADER_CAP_DFRACEXP_DLDEXP_SUPPORTED: case PIPE_SHADER_CAP_LDEXP_SUPPORTED: - case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED: case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE: return false; case PIPE_SHADER_CAP_SUPPORTED_IRS: @@ -420,8 +419,6 @@ etna_screen_get_shader_param(struct pipe_screen *pscreen, return 32; case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS: case PIPE_SHADER_CAP_MAX_SHADER_IMAGES: - case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD: - case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS: case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS: case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS: return 0; diff --git a/src/gallium/drivers/freedreno/freedreno_screen.c b/src/gallium/drivers/freedreno/freedreno_screen.c index 1106aa51fb0..04aaf6cf78a 100644 --- a/src/gallium/drivers/freedreno/freedreno_screen.c +++ b/src/gallium/drivers/freedreno/freedreno_screen.c @@ -647,11 +647,8 @@ fd_screen_get_shader_param(struct pipe_screen *pscreen, case PIPE_SHADER_CAP_DROUND_SUPPORTED: case PIPE_SHADER_CAP_DFRACEXP_DLDEXP_SUPPORTED: case PIPE_SHADER_CAP_LDEXP_SUPPORTED: - case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED: case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE: case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS: - case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD: - case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS: case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS: return 0; case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED: diff --git a/src/gallium/drivers/i915/i915_screen.c b/src/gallium/drivers/i915/i915_screen.c index 08d3b77d782..61988a52f54 100644 --- a/src/gallium/drivers/i915/i915_screen.c +++ b/src/gallium/drivers/i915/i915_screen.c @@ -362,12 +362,9 @@ i915_get_shader_param(struct pipe_screen *screen, enum pipe_shader_type shader, case PIPE_SHADER_CAP_DROUND_SUPPORTED: case PIPE_SHADER_CAP_DFRACEXP_DLDEXP_SUPPORTED: case PIPE_SHADER_CAP_LDEXP_SUPPORTED: - case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED: case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE: case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS: case PIPE_SHADER_CAP_MAX_SHADER_IMAGES: - case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD: - case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS: case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS: case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS: return 0; diff --git a/src/gallium/drivers/iris/iris_screen.c b/src/gallium/drivers/iris/iris_screen.c index 71bec2c1c65..180de3b9250 100644 --- a/src/gallium/drivers/iris/iris_screen.c +++ b/src/gallium/drivers/iris/iris_screen.c @@ -521,10 +521,7 @@ iris_get_shader_param(struct pipe_screen *pscreen, case PIPE_SHADER_CAP_DROUND_SUPPORTED: case PIPE_SHADER_CAP_LDEXP_SUPPORTED: return 1; - case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD: - case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS: case PIPE_SHADER_CAP_DFRACEXP_DLDEXP_SUPPORTED: - case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED: case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE: case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED: case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT: diff --git a/src/gallium/drivers/nouveau/nv30/nv30_screen.c b/src/gallium/drivers/nouveau/nv30/nv30_screen.c index 9404a030790..7240e932335 100644 --- a/src/gallium/drivers/nouveau/nv30/nv30_screen.c +++ b/src/gallium/drivers/nouveau/nv30/nv30_screen.c @@ -370,12 +370,9 @@ nv30_screen_get_shader_param(struct pipe_screen *pscreen, case PIPE_SHADER_CAP_DROUND_SUPPORTED: case PIPE_SHADER_CAP_DFRACEXP_DLDEXP_SUPPORTED: case PIPE_SHADER_CAP_LDEXP_SUPPORTED: - case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED: case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE: case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS: case PIPE_SHADER_CAP_MAX_SHADER_IMAGES: - case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD: - case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS: case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS: case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS: return 0; @@ -428,12 +425,9 @@ nv30_screen_get_shader_param(struct pipe_screen *pscreen, case PIPE_SHADER_CAP_DROUND_SUPPORTED: case PIPE_SHADER_CAP_DFRACEXP_DLDEXP_SUPPORTED: case PIPE_SHADER_CAP_LDEXP_SUPPORTED: - case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED: case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE: case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS: case PIPE_SHADER_CAP_MAX_SHADER_IMAGES: - case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD: - case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS: case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS: case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS: return 0; diff --git a/src/gallium/drivers/nouveau/nv50/nv50_screen.c b/src/gallium/drivers/nouveau/nv50/nv50_screen.c index 43e09ddffa5..220827ea203 100644 --- a/src/gallium/drivers/nouveau/nv50/nv50_screen.c +++ b/src/gallium/drivers/nouveau/nv50/nv50_screen.c @@ -384,7 +384,6 @@ nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_FRAGMENT_SHADER_INTERLOCK: case PIPE_CAP_CS_DERIVED_SYSTEM_VALUES_SUPPORTED: case PIPE_CAP_FBFETCH_COHERENT: - case PIPE_CAP_TGSI_SKIP_SHRINK_IO_ARRAYS: case PIPE_CAP_IMAGE_ATOMIC_INC_WRAP: case PIPE_CAP_DEMOTE_TO_HELPER_INVOCATION: case PIPE_CAP_TGSI_TG4_COMPONENT_IN_SWIZZLE: @@ -507,8 +506,6 @@ nv50_screen_get_shader_param(struct pipe_screen *pscreen, return 0; /* please inline, or provide function declarations */ case PIPE_SHADER_CAP_INTEGERS: return 1; - case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS: - return 1; case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS: /* The chip could handle more sampler views than samplers */ case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS: @@ -526,9 +523,7 @@ nv50_screen_get_shader_param(struct pipe_screen *pscreen, case PIPE_SHADER_CAP_DROUND_SUPPORTED: case PIPE_SHADER_CAP_DFRACEXP_DLDEXP_SUPPORTED: case PIPE_SHADER_CAP_LDEXP_SUPPORTED: - case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED: case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE: - case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD: case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS: case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS: return 0; diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c index df75e850559..8a875fd4cc0 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c @@ -413,7 +413,6 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_FRAGMENT_SHADER_INTERLOCK: case PIPE_CAP_CS_DERIVED_SYSTEM_VALUES_SUPPORTED: case PIPE_CAP_FBFETCH_COHERENT: - case PIPE_CAP_TGSI_SKIP_SHRINK_IO_ARRAYS: case PIPE_CAP_TGSI_TG4_COMPONENT_IN_SWIZZLE: case PIPE_CAP_OPENCL_INTEGER_FUNCTIONS: /* could be done */ case PIPE_CAP_INTEGER_MULTIPLY_32X16: /* could be done */ @@ -543,14 +542,9 @@ nvc0_screen_get_shader_param(struct pipe_screen *pscreen, return 1; case PIPE_SHADER_CAP_DROUND_SUPPORTED: return 1; - case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED: - return 1; - case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS: - return 1; case PIPE_SHADER_CAP_DFRACEXP_DLDEXP_SUPPORTED: case PIPE_SHADER_CAP_LDEXP_SUPPORTED: case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE: - case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD: case PIPE_SHADER_CAP_INT64_ATOMICS: case PIPE_SHADER_CAP_FP16: case PIPE_SHADER_CAP_FP16_DERIVATIVES: diff --git a/src/gallium/drivers/panfrost/pan_screen.c b/src/gallium/drivers/panfrost/pan_screen.c index b6e40b1db3b..deb1f392f1c 100644 --- a/src/gallium/drivers/panfrost/pan_screen.c +++ b/src/gallium/drivers/panfrost/pan_screen.c @@ -424,7 +424,6 @@ panfrost_get_shader_param(struct pipe_screen *screen, case PIPE_SHADER_CAP_DROUND_SUPPORTED: case PIPE_SHADER_CAP_DFRACEXP_DLDEXP_SUPPORTED: case PIPE_SHADER_CAP_LDEXP_SUPPORTED: - case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED: case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE: return 0; @@ -451,8 +450,6 @@ panfrost_get_shader_param(struct pipe_screen *screen, case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT: case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS: case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS: - case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS: - case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD: return 0; default: diff --git a/src/gallium/drivers/r300/r300_screen.c b/src/gallium/drivers/r300/r300_screen.c index 98be109a217..8027b3cef51 100644 --- a/src/gallium/drivers/r300/r300_screen.c +++ b/src/gallium/drivers/r300/r300_screen.c @@ -314,11 +314,8 @@ static int r300_get_shader_param(struct pipe_screen *pscreen, case PIPE_SHADER_CAP_DROUND_SUPPORTED: case PIPE_SHADER_CAP_DFRACEXP_DLDEXP_SUPPORTED: case PIPE_SHADER_CAP_LDEXP_SUPPORTED: - case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED: case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS: case PIPE_SHADER_CAP_MAX_SHADER_IMAGES: - case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD: - case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS: case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS: case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS: return 0; @@ -410,11 +407,8 @@ static int r300_get_shader_param(struct pipe_screen *pscreen, case PIPE_SHADER_CAP_DROUND_SUPPORTED: case PIPE_SHADER_CAP_DFRACEXP_DLDEXP_SUPPORTED: case PIPE_SHADER_CAP_LDEXP_SUPPORTED: - case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED: case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS: case PIPE_SHADER_CAP_MAX_SHADER_IMAGES: - case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD: - case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS: case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS: case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS: return 0; diff --git a/src/gallium/drivers/r600/r600_pipe.c b/src/gallium/drivers/r600/r600_pipe.c index acc2a8b94ea..d2fc3fce6dc 100644 --- a/src/gallium/drivers/r600/r600_pipe.c +++ b/src/gallium/drivers/r600/r600_pipe.c @@ -645,18 +645,9 @@ static int r600_get_shader_param(struct pipe_screen* pscreen, } return ir; } - case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED: - if (rscreen->b.family == CHIP_ARUBA || - rscreen->b.family == CHIP_CAYMAN || - rscreen->b.family == CHIP_CYPRESS || - rscreen->b.family == CHIP_HEMLOCK) - return 1; - return 0; case PIPE_SHADER_CAP_DROUND_SUPPORTED: case PIPE_SHADER_CAP_DFRACEXP_DLDEXP_SUPPORTED: case PIPE_SHADER_CAP_LDEXP_SUPPORTED: - case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD: - case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS: return 0; case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS: case PIPE_SHADER_CAP_MAX_SHADER_IMAGES: diff --git a/src/gallium/drivers/radeonsi/si_get.c b/src/gallium/drivers/radeonsi/si_get.c index 99f67128db8..5bef7a4d014 100644 --- a/src/gallium/drivers/radeonsi/si_get.c +++ b/src/gallium/drivers/radeonsi/si_get.c @@ -437,8 +437,6 @@ static int si_get_shader_param(struct pipe_screen *pscreen, enum pipe_shader_typ return 0; case PIPE_SHADER_CAP_PREFERRED_IR: return PIPE_SHADER_IR_NIR; - case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD: - return 4; case PIPE_SHADER_CAP_SUPPORTED_IRS: if (shader == PIPE_SHADER_COMPUTE) { @@ -457,9 +455,7 @@ static int si_get_shader_param(struct pipe_screen *pscreen, enum pipe_shader_typ case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR: case PIPE_SHADER_CAP_INTEGERS: case PIPE_SHADER_CAP_INT64_ATOMICS: - case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED: case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE: - case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS: case PIPE_SHADER_CAP_DROUND_SUPPORTED: case PIPE_SHADER_CAP_LDEXP_SUPPORTED: case PIPE_SHADER_CAP_DFRACEXP_DLDEXP_SUPPORTED: diff --git a/src/gallium/drivers/svga/svga_screen.c b/src/gallium/drivers/svga/svga_screen.c index 80721d33ea2..3feb253f669 100644 --- a/src/gallium/drivers/svga/svga_screen.c +++ b/src/gallium/drivers/svga/svga_screen.c @@ -548,12 +548,9 @@ vgpu9_get_shader_param(struct pipe_screen *screen, case PIPE_SHADER_CAP_DROUND_SUPPORTED: case PIPE_SHADER_CAP_DFRACEXP_DLDEXP_SUPPORTED: case PIPE_SHADER_CAP_LDEXP_SUPPORTED: - case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED: case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE: case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS: case PIPE_SHADER_CAP_MAX_SHADER_IMAGES: - case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD: - case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS: case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS: case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS: return 0; @@ -619,12 +616,9 @@ vgpu9_get_shader_param(struct pipe_screen *screen, case PIPE_SHADER_CAP_DROUND_SUPPORTED: case PIPE_SHADER_CAP_DFRACEXP_DLDEXP_SUPPORTED: case PIPE_SHADER_CAP_LDEXP_SUPPORTED: - case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED: case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE: case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS: case PIPE_SHADER_CAP_MAX_SHADER_IMAGES: - case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD: - case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS: case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS: case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS: return 0; @@ -739,8 +733,6 @@ vgpu10_get_shader_param(struct pipe_screen *screen, * the TGIS instruction into other instructions we do support. */ return 0; - case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED: - return sws->have_sm5; case PIPE_SHADER_CAP_MAX_SHADER_IMAGES: return sws->have_gl43 ? SVGA_MAX_IMAGES : 0; @@ -753,8 +745,6 @@ vgpu10_get_shader_param(struct pipe_screen *screen, return sws->have_gl43 ? SVGA_MAX_ATOMIC_BUFFERS : 0; case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE: - case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD: - case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS: case PIPE_SHADER_CAP_INT64_ATOMICS: return 0; case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT: diff --git a/src/gallium/drivers/svga/svga_tgsi_vgpu10.c b/src/gallium/drivers/svga/svga_tgsi_vgpu10.c index 362bbf637a4..56d2e179284 100644 --- a/src/gallium/drivers/svga/svga_tgsi_vgpu10.c +++ b/src/gallium/drivers/svga/svga_tgsi_vgpu10.c @@ -10962,7 +10962,7 @@ emit_instruction(struct svga_shader_emitter_v10 *emit, /* The following opcodes should never be seen here. We return zero * for all the PIPE_CAP_TGSI_DROUND_SUPPORTED, DFRACEXP_DLDEXP_SUPPORTED, - * FMA_SUPPORTED, LDEXP_SUPPORTED queries. + * LDEXP_SUPPORTED queries. */ case TGSI_OPCODE_LDEXP: case TGSI_OPCODE_DSSG: diff --git a/src/gallium/drivers/v3d/v3d_screen.c b/src/gallium/drivers/v3d/v3d_screen.c index f7477a82271..8ef201cee6b 100644 --- a/src/gallium/drivers/v3d/v3d_screen.c +++ b/src/gallium/drivers/v3d/v3d_screen.c @@ -431,7 +431,6 @@ v3d_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader, case PIPE_SHADER_CAP_DROUND_SUPPORTED: case PIPE_SHADER_CAP_DFRACEXP_DLDEXP_SUPPORTED: case PIPE_SHADER_CAP_LDEXP_SUPPORTED: - case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED: case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE: case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED: case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS: @@ -469,9 +468,6 @@ v3d_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader, case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT: /* We use NIR's loop unrolling */ return 0; - case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD: - case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS: - return 0; default: fprintf(stderr, "unknown shader param %d\n", param); return 0; diff --git a/src/gallium/drivers/vc4/vc4_screen.c b/src/gallium/drivers/vc4/vc4_screen.c index 0116ef2bdc8..fe1425894ec 100644 --- a/src/gallium/drivers/vc4/vc4_screen.c +++ b/src/gallium/drivers/vc4/vc4_screen.c @@ -302,7 +302,6 @@ vc4_screen_get_shader_param(struct pipe_screen *pscreen, case PIPE_SHADER_CAP_DROUND_SUPPORTED: case PIPE_SHADER_CAP_DFRACEXP_DLDEXP_SUPPORTED: case PIPE_SHADER_CAP_LDEXP_SUPPORTED: - case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED: case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE: return 0; case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS: @@ -316,8 +315,6 @@ vc4_screen_get_shader_param(struct pipe_screen *pscreen, return 32; case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS: case PIPE_SHADER_CAP_MAX_SHADER_IMAGES: - case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD: - case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS: case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS: case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS: return 0; diff --git a/src/gallium/drivers/virgl/virgl_screen.c b/src/gallium/drivers/virgl/virgl_screen.c index 455f71d9650..19c816a595d 100644 --- a/src/gallium/drivers/virgl/virgl_screen.c +++ b/src/gallium/drivers/virgl/virgl_screen.c @@ -342,8 +342,6 @@ virgl_get_param(struct pipe_screen *screen, enum pipe_cap param) case PIPE_CAP_DEST_SURFACE_SRGB_CONTROL: return (vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_SRGB_WRITE_CONTROL) || (vscreen->caps.caps.v2.host_feature_check_version < 1); - case PIPE_CAP_TGSI_SKIP_SHRINK_IO_ARRAYS: - return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_INDIRECT_INPUT_ADDR; case PIPE_CAP_SHAREABLE_SHADERS: /* Shader creation emits the shader through the context's command buffer * in virgl_encode_shader_state(). @@ -444,8 +442,6 @@ virgl_get_shader_param(struct pipe_screen *screen, return vscreen->caps.caps.v2.max_atomic_counters[shader]; case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS: return vscreen->caps.caps.v2.max_atomic_counter_buffers[shader]; - case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD: - case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS: case PIPE_SHADER_CAP_INT64_ATOMICS: case PIPE_SHADER_CAP_FP16: case PIPE_SHADER_CAP_FP16_DERIVATIVES: diff --git a/src/gallium/drivers/zink/zink_screen.c b/src/gallium/drivers/zink/zink_screen.c index 007e43422c7..c9049a7513f 100644 --- a/src/gallium/drivers/zink/zink_screen.c +++ b/src/gallium/drivers/zink/zink_screen.c @@ -965,7 +965,6 @@ zink_get_shader_param(struct pipe_screen *pscreen, case PIPE_SHADER_CAP_DROUND_SUPPORTED: case PIPE_SHADER_CAP_DFRACEXP_DLDEXP_SUPPORTED: - case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED: return 0; /* not implemented */ case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE: @@ -1006,10 +1005,6 @@ zink_get_shader_param(struct pipe_screen *pscreen, ZINK_MAX_SHADER_IMAGES); return 0; - case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD: - case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS: - return 0; /* unsure */ - case PIPE_SHADER_CAP_LDEXP_SUPPORTED: case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS: case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS: diff --git a/src/gallium/include/pipe/p_defines.h b/src/gallium/include/pipe/p_defines.h index 4a8ce7e5be5..5e09f00cfad 100644 --- a/src/gallium/include/pipe/p_defines.h +++ b/src/gallium/include/pipe/p_defines.h @@ -942,7 +942,6 @@ enum pipe_cap PIPE_CAP_MAX_VARYINGS, PIPE_CAP_COMPUTE_GRID_INFO_LAST_BLOCK, PIPE_CAP_COMPUTE_SHADER_DERIVATIVES, - PIPE_CAP_TGSI_SKIP_SHRINK_IO_ARRAYS, PIPE_CAP_IMAGE_LOAD_FORMATTED, PIPE_CAP_IMAGE_STORE_FORMATTED, PIPE_CAP_THROTTLE, @@ -1102,14 +1101,11 @@ enum pipe_shader_cap PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS, PIPE_SHADER_CAP_DROUND_SUPPORTED, /* all rounding modes */ PIPE_SHADER_CAP_DFRACEXP_DLDEXP_SUPPORTED, - PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED, PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE, PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT, PIPE_SHADER_CAP_MAX_SHADER_BUFFERS, PIPE_SHADER_CAP_SUPPORTED_IRS, PIPE_SHADER_CAP_MAX_SHADER_IMAGES, - PIPE_SHADER_CAP_LOWER_IF_THRESHOLD, - PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS, PIPE_SHADER_CAP_LDEXP_SUPPORTED, PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS, PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS,