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r600: add support for getting the tiling config via drm ioctl (v2)

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Needed for the the 2D tiling span functions.

v2: rebase on new kernel, mesa changes

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
This commit is contained in:
Alex Deucher 2010-07-21 17:46:45 -04:00
parent 3095bc679d
commit e93d413a0d
1 changed files with 57 additions and 0 deletions
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57
src/mesa/drivers/dri/radeon/radeon_screen.c
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@ -213,6 +213,10 @@ static const GLuint __driNConfigOptions = 17;
static int getSwapInfo( __DRIdrawable *dPriv, __DRIswapInfo * sInfo );
#ifndef RADEON_INFO_TILE_CONFIG
#define RADEON_INFO_TILE_CONFIG 0x6
#endif
static int
radeonGetParam(__DRIscreen *sPriv, int param, void *value)
{
@ -232,6 +236,9 @@ radeonGetParam(__DRIscreen *sPriv, int param, void *value)
case RADEON_PARAM_NUM_Z_PIPES:
info.request = RADEON_INFO_NUM_Z_PIPES;
break;
case RADEON_INFO_TILE_CONFIG:
info.request = RADEON_INFO_TILE_CONFIG;
break;
default:
return -EINVAL;
}
@ -1320,6 +1327,56 @@ radeonCreateScreen2(__DRIscreen *sPriv)
else
screen->chip_flags |= RADEON_CLASS_R600;
/* r6xx+ tiling */
if (IS_R600_CLASS(screen) && (sPriv->drm_version.minor >= 5)) {
ret = radeonGetParam(sPriv, RADEON_INFO_TILE_CONFIG, &temp);
if (ret)
fprintf(stderr, "failed to get tiling info\n");
else {
screen->tile_config = temp;
screen->r7xx_bank_op = 0;
switch((screen->tile_config & 0xe) >> 1) {
case 0:
screen->num_channels = 1;
break;
case 1:
screen->num_channels = 2;
break;
case 2:
screen->num_channels = 4;
break;
case 3:
screen->num_channels = 8;
break;
default:
fprintf(stderr, "bad channels\n");
break;
}
switch((screen->tile_config & 0x30) >> 4) {
case 0:
screen->num_banks = 4;
break;
case 1:
screen->num_banks = 8;
break;
default:
fprintf(stderr, "bad banks\n");
break;
}
switch((screen->tile_config & 0xc0) >> 6) {
case 0:
screen->group_bytes = 256;
break;
case 1:
screen->group_bytes = 512;
break;
default:
fprintf(stderr, "bad group_bytes\n");
break;
}
}
}
if (IS_R300_CLASS(screen)) {
ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_GB_PIPES, &temp);
if (ret) {