fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-01-07 00:00:12 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 2

radv: introduce SHIFT/MASK for unpacking shader input args

Browse source 
Loosely based on RadeonSI, looks cleaner and safer to me. I will also
use that to pack fragment shader arguments.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23333>
This commit is contained in:
Samuel Pitoiset 2023-05-31 13:29:53 +02:00 • committed by Marge Bot
parent a90d96bb22
commit e8fe8ce4bc
3 changed files with 22 additions and 5 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

12
src/amd/vulkan/nir/radv_nir_lower_abi.c
View file

@ -30,6 +30,9 @@
#include "radv_shader.h"
#include "radv_shader_args.h"
#define GET_SGPR_FIELD_NIR(arg, field) \
ac_nir_unpack_arg(b, &s->args->ac, arg, field##__SHIFT, util_bitcount(field##__MASK))
typedef struct {
enum amd_gfx_level gfx_level;
const struct radv_shader_args *args;
@ -97,7 +100,8 @@ lower_abi_instr(nir_builder *b, nir_instr *instr, void *state)
case nir_intrinsic_load_tcs_num_patches_amd:
if (s->pl_key->dynamic_patch_control_points) {
if (stage == MESA_SHADER_TESS_CTRL) {
replacement = ac_nir_unpack_arg(b, &s->args->ac, s->args->tcs_offchip_layout, 6, 8);
replacement = GET_SGPR_FIELD_NIR(s->args->tcs_offchip_layout,
TCS_OFFCHIP_LAYOUT_NUM_PATCHES);
} else {
replacement = ac_nir_load_arg(b, &s->args->ac, s->args->tes_num_patches);
}
@ -162,7 +166,8 @@ lower_abi_instr(nir_builder *b, nir_instr *instr, void *state)
case nir_intrinsic_load_patch_vertices_in:
if (stage == MESA_SHADER_TESS_CTRL) {
if (s->pl_key->dynamic_patch_control_points) {
replacement = ac_nir_unpack_arg(b, &s->args->ac, s->args->tcs_offchip_layout, 0, 6);
replacement = GET_SGPR_FIELD_NIR(s->args->tcs_offchip_layout,
TCS_OFFCHIP_LAYOUT_PATCH_CONTROL_POINTS);
} else {
replacement = nir_imm_int(b, s->pl_key->tcs.tess_input_vertices);
}
@ -296,7 +301,8 @@ lower_abi_instr(nir_builder *b, nir_instr *instr, void *state)
nir_ssa_def *num_patches;
if (stage == MESA_SHADER_TESS_CTRL) {
num_patches = ac_nir_unpack_arg(b, &s->args->ac, s->args->tcs_offchip_layout, 6, 8);
num_patches = GET_SGPR_FIELD_NIR(s->args->tcs_offchip_layout,
TCS_OFFCHIP_LAYOUT_NUM_PATCHES);
} else {
num_patches = ac_nir_load_arg(b, &s->args->ac, s->args->tes_num_patches);
}

7
src/amd/vulkan/radv_cmd_buffer.c
View file

@ -2592,9 +2592,12 @@ radv_emit_patch_control_points(struct radv_cmd_buffer *cmd_buffer)
return;
assert(offchip->num_sgprs == 1);
unsigned tcs_offchip_layout =
SET_SGPR_FIELD(TCS_OFFCHIP_LAYOUT_PATCH_CONTROL_POINTS, d->vk.ts.patch_control_points) |
SET_SGPR_FIELD(TCS_OFFCHIP_LAYOUT_NUM_PATCHES, cmd_buffer->state.tess_num_patches);
base_reg = cmd_buffer->state.shaders[MESA_SHADER_TESS_CTRL]->info.user_data_0;
radeon_set_sh_reg(cmd_buffer->cs, base_reg + offchip->sgpr_idx * 4,
(cmd_buffer->state.tess_num_patches << 6) | d->vk.ts.patch_control_points);
radeon_set_sh_reg(cmd_buffer->cs, base_reg + offchip->sgpr_idx * 4, tcs_offchip_layout);
const struct radv_userdata_info *num_patches = radv_get_user_sgpr(
radv_get_shader(cmd_buffer->state.shaders, MESA_SHADER_TESS_EVAL), AC_UD_TES_NUM_PATCHES);

8
src/amd/vulkan/radv_shader.h
View file

@ -189,6 +189,14 @@ enum radv_ud_index {
AC_UD_MAX_UD = AC_UD_CS_MAX_UD,
};
#define SET_SGPR_FIELD(field, value) \
(((unsigned)(value) & field##__MASK) << field##__SHIFT)
#define TCS_OFFCHIP_LAYOUT_PATCH_CONTROL_POINTS__SHIFT 0
#define TCS_OFFCHIP_LAYOUT_PATCH_CONTROL_POINTS__MASK 0x3f
#define TCS_OFFCHIP_LAYOUT_NUM_PATCHES__SHIFT 6
#define TCS_OFFCHIP_LAYOUT_NUM_PATCHES__MASK 0xff
struct radv_streamout_info {
uint16_t num_outputs;
uint16_t strides[MAX_SO_BUFFERS];