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r600/sfn: Unify the handling of resource IDs in instruction
Fetch, GDS, Texture, and RAT instructions all use resources with a possible offset defined by the index register. Unify the handling of resource ID and the offset register for these instruction types. Signed-off-by: Gert Wollny <gert.wollny@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19300>
This commit is contained in:
Gert Wollny
Marge Bot
parent
da1477a934
commit
e8e420568d
12 changed files with 143 additions and 126 deletions
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@ -430,8 +430,7 @@ void AssamblerVisitor::visit(const TexInstr& tex_instr)
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{
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clear_states(sf_vtx | sf_alu);
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int sampler_offset = 0;
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auto addr = tex_instr.sampler_offset();
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auto addr = tex_instr.resource_offset();
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EBufferIndexMode index_mode = bim_none;
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if (addr)
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@ -446,8 +445,8 @@ void AssamblerVisitor::visit(const TexInstr& tex_instr)
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r600_bytecode_tex tex;
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memset(&tex, 0, sizeof(struct r600_bytecode_tex));
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tex.op = tex_instr.opcode();
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tex.sampler_id = tex_instr.sampler_id() + sampler_offset;
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tex.resource_id = tex_instr.resource_id() + sampler_offset;
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tex.sampler_id = tex_instr.resource_base();
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tex.resource_id = tex_instr.resource_id();
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tex.src_gpr = tex_instr.src().sel();
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tex.dst_gpr = tex_instr.dst().sel();
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tex.dst_sel_x = tex_instr.dest_swizzle(0);
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@ -666,7 +665,7 @@ void AssamblerVisitor::visit(const FetchInstr& fetch_instr)
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struct r600_bytecode_vtx vtx;
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memset(&vtx, 0, sizeof(vtx));
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vtx.op = fetch_instr.opcode();
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vtx.buffer_id = fetch_instr.resource_id();
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vtx.buffer_id = fetch_instr.resource_base();
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vtx.fetch_type = fetch_instr.fetch_type();
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vtx.src_gpr = fetch_instr.src().sel();
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vtx.src_sel_x = fetch_instr.src().chan();
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@ -759,10 +758,10 @@ void AssamblerVisitor::visit(const RatInstr& instr)
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if (m_ack_suggested /*&& instr.has_instr_flag(Instr::ack_rat_return_write)*/)
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emit_wait_ack();
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int rat_idx = instr.rat_id();
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int rat_idx = instr.resource_base();
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EBufferIndexMode rat_index_mode = bim_none;
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auto addr = instr.rat_id_offset();
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auto addr = instr.resource_offset();
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if (addr)
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rat_index_mode = emit_index_reg(*addr, 1);
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@ -925,7 +924,7 @@ void AssamblerVisitor::visit(const GDSInstr& instr)
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struct r600_bytecode_gds gds;
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bool indirect = false;
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auto addr = instr.uav_id();
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auto addr = instr.resource_offset();
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if (addr) {
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indirect = true;
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@ -936,7 +935,7 @@ void AssamblerVisitor::visit(const GDSInstr& instr)
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gds.op = ds_opcode_map.at(instr.opcode());
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gds.dst_gpr = instr.dest()->sel();
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gds.uav_id = instr.uav_base();
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gds.uav_id = instr.resource_base();
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gds.uav_index_mode = indirect ? bim_one : bim_none;
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gds.src_gpr = instr.src().sel();
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@ -188,7 +188,10 @@ void Instr::forward_set_blockid(int id, int index)
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}
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InstrWithVectorResult::InstrWithVectorResult(const RegisterVec4& dest,
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const RegisterVec4::Swizzle& dest_swizzle):
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const RegisterVec4::Swizzle& dest_swizzle,
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int resource_base,
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PRegister resource_offset):
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InstrWithResource(resource_base, resource_offset),
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m_dest(dest),
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m_dest_swizzle(dest_swizzle)
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{
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@ -425,6 +428,7 @@ void Block::lds_group_end()
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}
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InstrWithVectorResult::InstrWithVectorResult(const InstrWithVectorResult& orig):
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InstrWithResource(orig),
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m_dest(orig.m_dest),
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m_dest_swizzle(orig.m_dest_swizzle)
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{
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@ -241,9 +241,76 @@ private:
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int m_emitted_rat_instr{0};
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};
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class InstrWithVectorResult : public Instr {
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class InstrWithResource : public Instr {
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public:
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InstrWithVectorResult(const RegisterVec4& dest, const RegisterVec4::Swizzle& dest_swizzle);
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InstrWithResource(int base, PRegister offset) :
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m_base(base), m_offset(offset)
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{
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if (m_offset) {
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m_offset->add_use(this);
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}
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}
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bool replace_resource_offset(PRegister old_offset, PRegister new_offset) {
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if (m_offset && old_offset->equal_to(*m_offset)) {
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m_offset->del_use(this);
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m_offset = new_offset;
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m_offset->add_use(this);
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return true;
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}
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return false;
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}
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void set_resource_offset(PRegister offset) {
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if (m_offset)
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m_offset->del_use(this);
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m_offset = offset;
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if (m_offset) {
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m_offset->add_use(this);
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}
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}
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bool resource_is_equal(const InstrWithResource& other) const {
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if (m_base != other.m_base)
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return false;
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if (m_offset && other.m_offset)
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return m_offset->equal_to(*other.m_offset);
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return !m_offset && !other.m_offset;
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}
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auto resource_base() const {return m_base;}
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auto resource_offset() const {return m_offset;}
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auto buffer_index_mode() const -> EBufferIndexMode {
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if (!m_offset)
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return bim_none;
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switch (m_offset->sel()) {
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case 1: return bim_zero;
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case 2: return bim_one;
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default:
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unreachable("Invalid resource offset, scheduler must substitute registers");
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}
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}
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bool resource_ready(int block_id, int index) const {
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return !m_offset || m_offset->ready(block_id, index);
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}
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protected:
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void print_resource_offset(std::ostream& os) const {
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if (m_offset)
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os << " + " << *m_offset;
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}
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private:
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int m_base{0};
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PRegister m_offset{nullptr};
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};
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class InstrWithVectorResult : public InstrWithResource {
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public:
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InstrWithVectorResult(const RegisterVec4& dest,
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const RegisterVec4::Swizzle& dest_swizzle,
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int resource_base,
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PRegister resource_offset);
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void set_dest_swizzle(const RegisterVec4::Swizzle& swz) {m_dest_swizzle = swz;}
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int dest_swizzle(int i) const { return m_dest_swizzle[i];}
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@ -46,7 +46,7 @@ FetchInstr::FetchInstr(EVFetchInstr opcode,
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EVFetchEndianSwap endian_swap,
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uint32_t resource_id,
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PRegister resource_offset):
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InstrWithVectorResult(dst, dest_swizzle),
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InstrWithVectorResult(dst, dest_swizzle, resource_id, resource_offset),
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m_opcode(opcode),
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m_src(src),
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m_src_offset(src_offset),
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@ -54,8 +54,6 @@ FetchInstr::FetchInstr(EVFetchInstr opcode,
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m_data_format(data_format),
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m_num_format(num_format),
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m_endian_swap(endian_swap),
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m_resource_id(resource_id),
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m_resource_offset(resource_offset),
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m_mega_fetch_count(0),
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m_array_base(0),
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m_array_size(0),
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@ -83,9 +81,6 @@ FetchInstr::FetchInstr(EVFetchInstr opcode,
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if (m_src)
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m_src->add_use(this);
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if (m_resource_offset && m_resource_offset->as_register())
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m_resource_offset->as_register()->add_use(this);
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}
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void FetchInstr::accept(ConstInstrVisitor& visitor) const
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@ -115,10 +110,10 @@ bool FetchInstr::is_equal_to(const FetchInstr& rhs) const
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if (m_tex_flags != rhs.m_tex_flags)
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return false;
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if (m_resource_offset && rhs.m_resource_offset) {
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if (!m_resource_offset->equal_to(*rhs.m_resource_offset))
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if (resource_offset() && rhs.resource_offset()) {
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if (!resource_offset()->equal_to(*rhs.resource_offset()))
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return false;
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} else if (!(!!m_resource_offset == !!rhs.m_resource_offset))
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} else if (!(!!resource_offset() == !!rhs.resource_offset()))
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return false;
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return m_opcode == rhs.m_opcode &&
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@ -127,11 +122,11 @@ bool FetchInstr::is_equal_to(const FetchInstr& rhs) const
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m_data_format == rhs.m_data_format &&
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m_num_format == rhs.m_num_format &&
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m_endian_swap == rhs.m_endian_swap &&
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m_resource_id == rhs.m_resource_id &&
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m_mega_fetch_count == rhs.m_mega_fetch_count &&
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m_array_base == rhs.m_array_base &&
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m_array_size == rhs.m_array_size &&
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m_elm_size == rhs.m_elm_size;
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m_elm_size == rhs.m_elm_size &&
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resource_base() == rhs.resource_base();
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}
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bool FetchInstr::propagate_death()
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@ -153,12 +148,7 @@ bool FetchInstr::replace_source(PRegister old_src, PVirtualValue new_src)
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new_reg->add_use(this);
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success = true;
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}
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if (m_resource_offset && old_src->equal_to(*m_resource_offset)) {
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m_resource_offset->del_use(this);
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m_resource_offset = new_reg;
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new_reg->add_use(this);
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success = true;
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}
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success |= replace_resource_offset(old_src, new_reg);
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}
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return success;
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}
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@ -171,11 +161,8 @@ bool FetchInstr::do_ready() const
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}
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bool result = m_src && m_src->ready(block_id(), index());
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if (m_resource_offset) {
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auto r = m_resource_offset->as_register();
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if (r)
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result &= r->ready(block_id(), index());
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}
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if (resource_offset())
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result &= resource_offset()->ready(block_id(), index());
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return result;
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}
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@ -197,12 +184,9 @@ void FetchInstr::do_print(std::ostream& os) const
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}
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if (m_opcode != vc_read_scratch)
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os << " RID:" << m_resource_id;
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os << " RID:" << resource_base();
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if (m_resource_offset) {
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os << " + ";
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m_resource_offset->print(os);
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}
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print_resource_offset(os);
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if (!m_skip_print.test(ftype)) {
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switch (m_fetch_type) {
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@ -78,8 +78,7 @@ public:
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const auto& src() const {assert(m_src); return *m_src;}
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uint32_t src_offset() const {return m_src_offset;}
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uint32_t resource_id() const {return m_resource_id;}
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auto resource_offset() const {return m_resource_offset;}
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uint32_t resource_id() const __attribute__((deprecated)) {return resource_base();}
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EVFetchType fetch_type() const {return m_fetch_type;}
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EVTXDataFormat data_format() const {return m_data_format;}
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@ -140,9 +139,6 @@ private:
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EVFetchNumFormat m_num_format;
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EVFetchEndianSwap m_endian_swap;
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uint32_t m_resource_id;
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PRegister m_resource_offset;
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std::bitset<EFlags::unknown> m_tex_flags;
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std::bitset<EPrintSkip::count> m_skip_print;
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@ -35,19 +35,15 @@ namespace r600 {
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GDSInstr::GDSInstr(ESDOp op, Register *dest,
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const RegisterVec4& src, int uav_base,
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PRegister uav_id):
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InstrWithResource(uav_base, uav_id),
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m_op(op),
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m_dest(dest),
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m_src(src),
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m_uav_base(uav_base),
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m_uav_id(uav_id)
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m_src(src)
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{
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set_always_keep();
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m_src.add_use(this);
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m_dest->add_parent(this);
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if (m_uav_id)
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m_uav_id->add_use(this);
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}
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bool GDSInstr::is_equal_to(const GDSInstr& rhs) const
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@ -55,13 +51,12 @@ bool GDSInstr::is_equal_to(const GDSInstr& rhs) const
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#define NE(X) (X != rhs. X)
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if (NE(m_op) ||
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NE(m_src) ||
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NE(m_uav_base))
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NE(m_src))
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return false;
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sfn_value_equal(m_dest, rhs.m_dest);
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return sfn_value_equal(m_uav_id, rhs.m_uav_id);
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return resource_is_equal(rhs);
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}
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void GDSInstr::accept(ConstInstrVisitor& visitor) const
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@ -77,7 +72,7 @@ void GDSInstr::accept(InstrVisitor& visitor)
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bool GDSInstr::do_ready() const
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{
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return m_src.ready(block_id(), index()) &&
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(!m_uav_id || m_uav_id->ready(block_id(), index()));
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resource_ready(block_id(), index());
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}
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void GDSInstr::do_print(std::ostream& os) const
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@ -85,10 +80,9 @@ void GDSInstr::do_print(std::ostream& os) const
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os << "GDS " << lds_ops.at(m_op).name
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<< *m_dest;
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os << " " << m_src;
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os << " BASE:" << m_uav_base;
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os << " BASE:" << resource_base();
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if (m_uav_id)
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os << " UAV:" << *m_uav_id;
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print_resource_offset(os);
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}
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bool GDSInstr::emit_atomic_counter(nir_intrinsic_instr *intr, Shader& shader)
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@ -323,22 +317,18 @@ RatInstr::RatInstr(ECFOpCode cf_opcode, ERatOp rat_op,
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const RegisterVec4& data, const RegisterVec4& index,
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int rat_id, PRegister rat_id_offset,
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int burst_count, int comp_mask, int element_size):
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InstrWithResource(rat_id, rat_id_offset),
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m_cf_opcode(cf_opcode),
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m_rat_op(rat_op),
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m_data(data),
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m_index(index),
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m_rat_id_offset(rat_id_offset),
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m_rat_id(rat_id),
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m_burst_count(burst_count),
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m_comp_mask(comp_mask),
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m_element_size(element_size)
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{
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set_always_keep();
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m_data.add_use(this);
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m_index.add_use(this);
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if (m_rat_id_offset)
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m_rat_id_offset->add_use(this);
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}
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@ -375,9 +365,8 @@ bool RatInstr::do_ready() const
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void RatInstr::do_print(std::ostream& os) const
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{
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os << "MEM_RAT RAT " << m_rat_id;
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if (m_rat_id_offset)
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os << "+" << *m_rat_id_offset;
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os << "MEM_RAT RAT " << resource_base();
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print_resource_offset(os);
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os << " @" << m_index;
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os << " OP:" << m_rat_op << " " << m_data;
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os << " BC:" << m_burst_count
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@ -34,7 +34,7 @@ namespace r600 {
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class Shader;
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class GDSInstr : public Instr {
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class GDSInstr : public InstrWithResource {
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public:
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GDSInstr(ESDOp op, Register *dest,
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@ -54,9 +54,6 @@ public:
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const auto& dest() const { return m_dest;}
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auto& dest() { return m_dest;}
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auto uav_id() const {return m_uav_id;}
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auto uav_base() const {return m_uav_base;}
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static auto from_string(std::istream& is, ValueFactory& value_factory) -> Pointer;
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static bool emit_atomic_counter(nir_intrinsic_instr *intr, Shader& shader);
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@ -76,13 +73,11 @@ private:
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RegisterVec4 m_src;
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int m_uav_base{0};
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PRegister m_uav_id{nullptr};
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std::bitset<8> m_tex_flags;
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};
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class RatInstr : public Instr {
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class RatInstr : public InstrWithResource {
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public:
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enum ERatOp {
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@ -132,9 +127,6 @@ public:
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int rat_id, PRegister rat_id_offset,
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int burst_count, int comp_mask, int element_size);
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auto rat_id_offset() const { return m_rat_id_offset;}
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int rat_id() const { return m_rat_id;}
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ERatOp rat_op() const {return m_rat_op;}
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const auto& value() const { return m_data;}
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@ -186,9 +178,7 @@ private:
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|||
|
||||
RegisterVec4 m_data;
|
||||
RegisterVec4 m_index;
|
||||
PRegister m_rat_id_offset{nullptr};
|
||||
|
||||
int m_rat_id{0};
|
||||
int m_burst_count{0};
|
||||
int m_comp_mask{15};
|
||||
int m_element_size{3};
|
||||
|
|
|
|||
|
|
@ -39,20 +39,15 @@ using std::string;
|
|||
TexInstr::TexInstr(Opcode op, const RegisterVec4& dest,
|
||||
const RegisterVec4::Swizzle& dest_swizzle,
|
||||
const RegisterVec4& src, unsigned sid, unsigned rid,
|
||||
PVirtualValue sampler_offs):
|
||||
InstrWithVectorResult(dest, dest_swizzle),
|
||||
PRegister sampler_offs):
|
||||
InstrWithVectorResult(dest, dest_swizzle, sid, sampler_offs),
|
||||
m_opcode(op),
|
||||
m_src(src),
|
||||
m_sampler_offset(sampler_offs),
|
||||
m_inst_mode(0),
|
||||
m_sampler_id(sid),
|
||||
m_resource_id(rid)
|
||||
{
|
||||
memset(m_offset, 0, sizeof(m_offset));
|
||||
m_src.add_use(this);
|
||||
|
||||
if (m_sampler_offset && m_sampler_offset->as_register())
|
||||
m_sampler_offset->as_register()->add_use(this);
|
||||
}
|
||||
|
||||
void TexInstr::accept(ConstInstrVisitor& visitor) const
|
||||
|
|
@ -93,11 +88,11 @@ bool TexInstr::is_equal_to(const TexInstr& lhs) const
|
|||
if (m_src != lhs.m_src)
|
||||
return false;
|
||||
|
||||
if (m_sampler_offset && lhs.m_sampler_offset) {
|
||||
if (!m_sampler_offset->equal_to(*lhs.m_sampler_offset))
|
||||
if (resource_offset() && lhs.resource_offset()) {
|
||||
if (!resource_offset()->equal_to(*lhs.resource_offset()))
|
||||
return false;
|
||||
} else if ((m_sampler_offset && !lhs.m_sampler_offset) ||
|
||||
(!m_sampler_offset && lhs.m_sampler_offset))
|
||||
} else if ((resource_offset() && !lhs.resource_offset()) ||
|
||||
(!resource_offset() && lhs.resource_offset()))
|
||||
return false;
|
||||
|
||||
if (m_tex_flags != lhs.m_tex_flags)
|
||||
|
|
@ -108,7 +103,7 @@ bool TexInstr::is_equal_to(const TexInstr& lhs) const
|
|||
return false;
|
||||
}
|
||||
return m_inst_mode == lhs.m_inst_mode &&
|
||||
m_sampler_id == lhs.m_sampler_id &&
|
||||
resource_base() == lhs.resource_base() &&
|
||||
m_resource_id == lhs.m_resource_id;
|
||||
}
|
||||
|
||||
|
|
@ -129,8 +124,7 @@ bool TexInstr::do_ready() const
|
|||
return false;
|
||||
}
|
||||
|
||||
if (m_sampler_offset && m_sampler_offset->as_register() &&
|
||||
!m_sampler_offset->as_register()->ready(block_id(), index()))
|
||||
if (resource_offset() && !resource_offset()->ready(block_id(), index()))
|
||||
return false;
|
||||
return m_src.ready(block_id(), index());
|
||||
}
|
||||
|
|
@ -149,10 +143,10 @@ void TexInstr::do_print(std::ostream& os) const
|
|||
m_src.print(os);
|
||||
|
||||
os << " RID:" << m_resource_id
|
||||
<< " SID:" << m_sampler_id;
|
||||
<< " SID:" << resource_base();
|
||||
|
||||
if (m_sampler_offset)
|
||||
os << " SO:" << *m_sampler_offset;
|
||||
if (resource_offset())
|
||||
os << " SO:" << *resource_offset();
|
||||
|
||||
if (m_offset[0])
|
||||
os << " OX:" << m_offset[0];
|
||||
|
|
@ -318,7 +312,7 @@ void TexInstr::set_tex_param(const std::string& token)
|
|||
else if (token.substr(0,5) == "MODE:")
|
||||
set_inst_mode(int_from_string_with_prefix(token, "MODE:"));
|
||||
else if (token.substr(0,3) == "SO:")
|
||||
set_sampler_offset(VirtualValue::from_string(token.substr(3)));
|
||||
set_resource_offset(VirtualValue::from_string(token.substr(3))->as_register());
|
||||
else {
|
||||
std::cerr << "Token '" << token << "': ";
|
||||
unreachable("Unknown token in tex param");
|
||||
|
|
@ -407,13 +401,13 @@ void TexInstr::emit_set_gradients(nir_tex_instr* tex, int sampler_id,
|
|||
grad[0] = new TexInstr(set_gradient_h, empty_dst, {7,7,7,7}, src.ddx,
|
||||
sampler_id,
|
||||
sampler_id + R600_MAX_CONST_BUFFERS,
|
||||
src.sampler_offset);
|
||||
src.resource_offset);
|
||||
grad[0]->set_rect_coordinate_flags(tex);
|
||||
grad[0]->set_always_keep();
|
||||
|
||||
grad[1] = new TexInstr(set_gradient_v, empty_dst, {7,7,7,7}, src.ddy,
|
||||
sampler_id, sampler_id + R600_MAX_CONST_BUFFERS,
|
||||
src.sampler_offset);
|
||||
src.resource_offset);
|
||||
grad[1]->set_rect_coordinate_flags(tex);
|
||||
grad[1]->set_always_keep();
|
||||
irt->add_prepare_instr(grad[0]);
|
||||
|
|
@ -444,7 +438,7 @@ void TexInstr::emit_set_offsets(nir_tex_instr* tex, int sampler_id,
|
|||
auto set_ofs = new TexInstr(TexInstr::set_offsets, empty_dst, {7,7,7,7},
|
||||
ofs, sampler_id,
|
||||
sampler_id + R600_MAX_CONST_BUFFERS,
|
||||
src.sampler_offset);
|
||||
src.resource_offset);
|
||||
set_ofs->set_always_keep();
|
||||
irt->add_prepare_instr(set_ofs);
|
||||
}
|
||||
|
|
@ -485,7 +479,7 @@ bool TexInstr::emit_lowered_tex(nir_tex_instr* tex, Inputs& src, Shader& shader)
|
|||
}
|
||||
auto irt = new TexInstr(src.opcode, dst, dst_swz, src_coord, sampler.id,
|
||||
sampler.id + R600_MAX_CONST_BUFFERS,
|
||||
src.sampler_offset);
|
||||
src.resource_offset);
|
||||
|
||||
if (tex->op == nir_texop_txd)
|
||||
emit_set_gradients(tex, sampler.id, src, irt, shader);
|
||||
|
|
@ -514,8 +508,8 @@ bool TexInstr::emit_buf_txf(nir_tex_instr *tex, Inputs& src, Shader& shader)
|
|||
auto dst = vf.dest_vec4(tex->dest, pin_group);
|
||||
|
||||
PRegister tex_offset = nullptr;
|
||||
if (src.texture_offset)
|
||||
tex_offset = shader.emit_load_to_register(src.texture_offset);
|
||||
if (src.resource_offset)
|
||||
tex_offset = shader.emit_load_to_register(src.resource_offset);
|
||||
|
||||
auto *real_dst = &dst;
|
||||
RegisterVec4 tmp = vf.temp_vec4(pin_group);
|
||||
|
|
@ -559,8 +553,9 @@ bool TexInstr::emit_tex_texture_samples(nir_tex_instr* instr, Inputs& src, Shade
|
|||
|
||||
int res_id = R600_MAX_CONST_BUFFERS + instr->sampler_index;
|
||||
|
||||
// Fishy: should the zero be instr->sampler_index?
|
||||
auto ir = new TexInstr(src.opcode, dest, {3, 7, 7, 7}, help,
|
||||
0, res_id, src.sampler_offset);
|
||||
0, res_id, src.resource_offset);
|
||||
shader.emit_instruction(ir);
|
||||
return true;
|
||||
}
|
||||
|
|
@ -598,7 +593,7 @@ bool TexInstr::emit_tex_txs(nir_tex_instr *tex, Inputs& src,
|
|||
auto ir = new TexInstr(get_resinfo, dest, dest_swz, src_coord,
|
||||
sampler.id,
|
||||
sampler.id + R600_MAX_CONST_BUFFERS,
|
||||
src.sampler_offset);
|
||||
src.resource_offset);
|
||||
|
||||
ir->set_dest_swizzle(dest_swz);
|
||||
shader.emit_instruction(ir);
|
||||
|
|
@ -677,8 +672,8 @@ TexInstr::Inputs::Inputs(const nir_tex_instr& instr, ValueFactory& vf):
|
|||
offset(nullptr),
|
||||
gather_comp(nullptr),
|
||||
ms_index(nullptr),
|
||||
sampler_offset(nullptr),
|
||||
texture_offset(nullptr),
|
||||
resource_offset(nullptr),
|
||||
backend1(nullptr),
|
||||
backend2(nullptr),
|
||||
opcode(ld)
|
||||
|
|
@ -727,7 +722,7 @@ TexInstr::Inputs::Inputs(const nir_tex_instr& instr, ValueFactory& vf):
|
|||
texture_offset = vf.src(instr.src[i], 0);
|
||||
break;
|
||||
case nir_tex_src_sampler_offset:
|
||||
sampler_offset = vf.src(instr.src[i], 0);
|
||||
resource_offset = vf.src(instr.src[i], 0)->as_register();
|
||||
break;
|
||||
case nir_tex_src_backend1:
|
||||
backend1 = &instr.src[i].src;
|
||||
|
|
|
|||
|
|
@ -98,8 +98,8 @@ public:
|
|||
nir_src *offset;
|
||||
PVirtualValue gather_comp;
|
||||
PVirtualValue ms_index;
|
||||
PVirtualValue sampler_offset;
|
||||
PVirtualValue texture_offset;
|
||||
PRegister resource_offset;
|
||||
nir_src *backend1;
|
||||
nir_src *backend2;
|
||||
|
||||
|
|
@ -113,7 +113,7 @@ public:
|
|||
TexInstr(Opcode op, const RegisterVec4& dest,
|
||||
const RegisterVec4::Swizzle& dest_swizzle,
|
||||
const RegisterVec4& src, unsigned sid, unsigned rid,
|
||||
PVirtualValue sampler_offs = nullptr);
|
||||
PRegister sampler_offs = nullptr);
|
||||
|
||||
TexInstr(const TexInstr& orig) = delete;
|
||||
TexInstr(const TexInstr&& orig) = delete;
|
||||
|
|
@ -127,7 +127,6 @@ public:
|
|||
auto& src() {return m_src;}
|
||||
|
||||
unsigned opcode() const {return m_opcode;}
|
||||
unsigned sampler_id() const {return m_sampler_id;}
|
||||
unsigned resource_id() const {return m_resource_id;}
|
||||
|
||||
void set_offset(unsigned index, int32_t val);
|
||||
|
|
@ -139,9 +138,6 @@ public:
|
|||
void set_tex_flag(Flags flag) {m_tex_flags.set(flag);}
|
||||
bool has_tex_flag(Flags flag) const {return m_tex_flags.test(flag);}
|
||||
|
||||
void set_sampler_offset(PVirtualValue ofs) {m_sampler_offset = ofs;}
|
||||
auto* sampler_offset() const {return m_sampler_offset;}
|
||||
|
||||
void set_gather_comp(int cmp);
|
||||
bool is_equal_to(const TexInstr& lhs) const;
|
||||
|
||||
|
|
@ -188,11 +184,9 @@ private:
|
|||
Opcode m_opcode;
|
||||
|
||||
RegisterVec4 m_src;
|
||||
PVirtualValue m_sampler_offset;
|
||||
std::bitset<num_tex_flag> m_tex_flags;
|
||||
int m_offset[3];
|
||||
int m_inst_mode;
|
||||
unsigned m_sampler_id;
|
||||
unsigned m_resource_id;
|
||||
|
||||
static const std::map<Opcode, std::string> s_opcode_map;
|
||||
|
|
|
|||
|
|
@ -255,9 +255,8 @@ void LiveRangeInstrVisitor::visit(TexInstr *instr)
|
|||
auto src = instr->src();
|
||||
record_read(src, LiveRangeEntry::use_unspecified);
|
||||
|
||||
if (instr->sampler_offset() && instr->sampler_offset()->as_register())
|
||||
record_read(instr->sampler_offset()->as_register(), LiveRangeEntry::use_unspecified);
|
||||
|
||||
if (instr->resource_offset())
|
||||
record_read(instr->resource_offset(), LiveRangeEntry::use_unspecified);
|
||||
}
|
||||
|
||||
void LiveRangeInstrVisitor::visit(ExportInstr *instr)
|
||||
|
|
@ -347,8 +346,8 @@ void LiveRangeInstrVisitor::visit(GDSInstr *instr)
|
|||
{
|
||||
sfn_log << SfnLog::merge << "Visit " << *instr << "\n";
|
||||
record_read(instr->src(), LiveRangeEntry::use_unspecified);
|
||||
if (instr->uav_id())
|
||||
record_read(instr->uav_id(), LiveRangeEntry::use_unspecified);
|
||||
if (instr->resource_offset())
|
||||
record_read(instr->resource_offset(), LiveRangeEntry::use_unspecified);
|
||||
record_write(instr->dest());
|
||||
}
|
||||
|
||||
|
|
@ -358,7 +357,7 @@ void LiveRangeInstrVisitor::visit(RatInstr *instr)
|
|||
record_read(instr->value(), LiveRangeEntry::use_unspecified);
|
||||
record_read(instr->addr(), LiveRangeEntry::use_unspecified);
|
||||
|
||||
auto idx = instr->rat_id_offset();
|
||||
auto idx = instr->resource_offset();
|
||||
if (idx)
|
||||
record_read(idx, LiveRangeEntry::use_unspecified);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -409,7 +409,7 @@ TEST_F(InstrTest, test_tex_basic)
|
|||
EXPECT_EQ(tex.dest_swizzle(i), i);
|
||||
}
|
||||
|
||||
EXPECT_EQ(tex.sampler_id(), 1);
|
||||
EXPECT_EQ(tex.resource_base(), 1);
|
||||
EXPECT_EQ(tex.resource_id(), 17);
|
||||
|
||||
EXPECT_TRUE(tex.end_group());
|
||||
|
|
@ -443,7 +443,7 @@ TEST_F(InstrTest, test_tex_basic)
|
|||
|
||||
EXPECT_EQ(tex.inst_mode(), 0);
|
||||
|
||||
EXPECT_FALSE(tex.sampler_offset());
|
||||
EXPECT_FALSE(tex.resource_offset());
|
||||
|
||||
tex.set_dest_swizzle({4, 7, 0, 1});
|
||||
EXPECT_EQ(tex.dest_swizzle(0), 4);
|
||||
|
|
@ -487,7 +487,7 @@ TEST_F(InstrTest, test_tex_gather4)
|
|||
EXPECT_EQ(tex.dest_swizzle(i), i);
|
||||
}
|
||||
|
||||
EXPECT_EQ(tex.sampler_id(), 2);
|
||||
EXPECT_EQ(tex.resource_base(), 2);
|
||||
EXPECT_EQ(tex.resource_id(), 19);
|
||||
|
||||
for (int i = 0; i < 3; ++i)
|
||||
|
|
@ -625,7 +625,7 @@ TEST_F(InstrTest, test_fetch_basic)
|
|||
EXPECT_EQ(fetch.src(), Register(201, 2, pin_none));
|
||||
EXPECT_EQ(fetch.src_offset(), 0);
|
||||
|
||||
EXPECT_EQ(fetch.resource_id(), 1);
|
||||
EXPECT_EQ(fetch.resource_base(), 1);
|
||||
EXPECT_FALSE(fetch.resource_offset());
|
||||
|
||||
EXPECT_EQ(fetch.fetch_type(), vertex_data);
|
||||
|
|
@ -758,7 +758,7 @@ TEST_F(InstrTest, test_fetch_basic2)
|
|||
EXPECT_EQ(fetch.src(), Register(202, 3, pin_none));
|
||||
EXPECT_EQ(fetch.src_offset(), 1);
|
||||
|
||||
EXPECT_EQ(fetch.resource_id(), 3);
|
||||
EXPECT_EQ(fetch.resource_base(), 3);
|
||||
EXPECT_EQ(*fetch.resource_offset(), Register(300, 1, pin_none));
|
||||
|
||||
EXPECT_EQ(fetch.fetch_type(), no_index_offset);
|
||||
|
|
|
|||
|
|
@ -389,8 +389,8 @@ TEST_F(TestInstrFromString, test_tex_sampler_with_offset)
|
|||
{
|
||||
add_dest_vec4_from_string("R2002.xyzw");
|
||||
auto init = std::string("TEX SAMPLE R1001.xyzw : R2002.xyzw RID:7 SID:27 SO:R200.z NNNN");
|
||||
TexInstr expect(TexInstr::sample, RegisterVec4(1001), {0,1,2,3}, RegisterVec4(2002), 27, 7);
|
||||
expect.set_sampler_offset(new Register( 200, 2, pin_none));
|
||||
TexInstr expect(TexInstr::sample, RegisterVec4(1001), {0,1,2,3},
|
||||
RegisterVec4(2002), 27, 7, new Register( 200, 2, pin_none));
|
||||
check(init, expect);
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue