diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 347c9505132..e4327c946fc 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -5375,9 +5375,11 @@ radv_emit_alpha_to_coverage_enable(struct radv_cmd_buffer *cmd_buffer)
 
    radeon_begin(cmd_buffer->cs);
    if (pdev->info.gfx_level >= GFX12) {
-      radeon_set_context_reg(R_02807C_DB_ALPHA_TO_MASK, db_alpha_to_mask);
+      radeon_opt_set_context_reg(cmd_buffer, R_02807C_DB_ALPHA_TO_MASK, RADV_TRACKED_DB_ALPHA_TO_MASK,
+                                 db_alpha_to_mask);
    } else {
-      radeon_set_context_reg(R_028B70_DB_ALPHA_TO_MASK, db_alpha_to_mask);
+      radeon_opt_set_context_reg(cmd_buffer, R_028B70_DB_ALPHA_TO_MASK, RADV_TRACKED_DB_ALPHA_TO_MASK,
+                                 db_alpha_to_mask);
    }
    radeon_end();
 }
@@ -5386,11 +5388,11 @@ static void
 radv_emit_sample_mask(struct radv_cmd_buffer *cmd_buffer)
 {
    const struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
+   const uint32_t sample_mask = d->vk.ms.sample_mask | ((uint32_t)d->vk.ms.sample_mask << 16);
 
    radeon_begin(cmd_buffer->cs);
-   radeon_set_context_reg_seq(R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
-   radeon_emit(d->vk.ms.sample_mask | ((uint32_t)d->vk.ms.sample_mask << 16));
-   radeon_emit(d->vk.ms.sample_mask | ((uint32_t)d->vk.ms.sample_mask << 16));
+   radeon_opt_set_context_reg2(cmd_buffer, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, RADV_TRACKED_PA_SC_AA_MASK_X0Y0_X1Y0,
+                               sample_mask, sample_mask);
    radeon_end();
 }
 
@@ -5697,22 +5699,25 @@ radv_emit_msaa_state(struct radv_cmd_buffer *cmd_buffer)
    radeon_begin(cmd_buffer->cs);
 
    if (pdev->info.gfx_level >= GFX12) {
-      radeon_set_context_reg(R_028C5C_PA_SC_SAMPLE_PROPERTIES, S_028C5C_MAX_SAMPLE_DIST(max_sample_dist));
+      radeon_opt_set_context_reg(cmd_buffer, R_028C5C_PA_SC_SAMPLE_PROPERTIES, RADV_TRACKED_PA_SC_SAMPLE_PROPERTIES,
+                                 S_028C5C_MAX_SAMPLE_DIST(max_sample_dist));
 
-      radeon_set_context_reg(R_028078_DB_EQAA, db_eqaa);
-      radeon_set_context_reg(R_028C54_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL, pa_sc_conservative_rast);
+      radeon_opt_set_context_reg(cmd_buffer, R_028078_DB_EQAA, RADV_TRACKED_DB_EQAA, db_eqaa);
+      radeon_opt_set_context_reg(cmd_buffer, R_028C54_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
+                                 RADV_TRACKED_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL, pa_sc_conservative_rast);
    } else {
-      radeon_set_context_reg(R_028804_DB_EQAA, db_eqaa);
+      radeon_opt_set_context_reg(cmd_buffer, R_028804_DB_EQAA, RADV_TRACKED_DB_EQAA, db_eqaa);
 
       if (pdev->info.gfx_level >= GFX9)
-         radeon_set_context_reg(R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL, pa_sc_conservative_rast);
+         radeon_opt_set_context_reg(cmd_buffer, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
+                                    RADV_TRACKED_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL, pa_sc_conservative_rast);
    }
 
-   radeon_set_context_reg(R_028BE0_PA_SC_AA_CONFIG, pa_sc_aa_config);
-   radeon_set_context_reg(R_028A48_PA_SC_MODE_CNTL_0, S_028A48_ALTERNATE_RBS_PER_TILE(pdev->info.gfx_level >= GFX9) |
-                                                         S_028A48_VPORT_SCISSOR_ENABLE(1) |
-                                                         S_028A48_LINE_STIPPLE_ENABLE(d->vk.rs.line.stipple.enable) |
-                                                         S_028A48_MSAA_ENABLE(rasterization_samples > 1));
+   radeon_opt_set_context_reg(cmd_buffer, R_028BE0_PA_SC_AA_CONFIG, RADV_TRACKED_PA_SC_AA_CONFIG, pa_sc_aa_config);
+   radeon_opt_set_context_reg(
+      cmd_buffer, R_028A48_PA_SC_MODE_CNTL_0, RADV_TRACKED_PA_SC_MODE_CNTL_0,
+      S_028A48_ALTERNATE_RBS_PER_TILE(pdev->info.gfx_level >= GFX9) | S_028A48_VPORT_SCISSOR_ENABLE(1) |
+         S_028A48_LINE_STIPPLE_ENABLE(d->vk.rs.line.stipple.enable) | S_028A48_MSAA_ENABLE(rasterization_samples > 1));
    radeon_end();
 }
 
diff --git a/src/amd/vulkan/radv_cmd_buffer.h b/src/amd/vulkan/radv_cmd_buffer.h
index 0b51042ca83..94a2e2368ba 100644
--- a/src/amd/vulkan/radv_cmd_buffer.h
+++ b/src/amd/vulkan/radv_cmd_buffer.h
@@ -330,6 +330,16 @@ enum radv_tracked_reg {
    RADV_TRACKED_PA_SU_LINE_CNTL,
    RADV_TRACKED_PA_SU_SC_MODE_CNTL,
 
+   /* 2 consecutive registers */
+   RADV_TRACKED_PA_SC_AA_MASK_X0Y0_X1Y0,
+
+   RADV_TRACKED_DB_EQAA,
+   RADV_TRACKED_DB_ALPHA_TO_MASK,
+   RADV_TRACKED_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL, /* GFX9+ */
+   RADV_TRACKED_PA_SC_AA_CONFIG,
+   RADV_TRACKED_PA_SC_MODE_CNTL_0,
+   RADV_TRACKED_PA_SC_SAMPLE_PROPERTIES, /* GFX12+ */
+
    RADV_NUM_ALL_TRACKED_REGS,
 };