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util: Improve has_sse has_sse2 has_sse3 has_sse4_1 has_avx disable handling

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This is the prepare for following changes：

* Handling GALLIUM_NOSSE in u_cpu_detect.c
* Handling LP_FORCE_SSE2 and LP_NATIVE_VECTOR_WIDTH in u_cpu_detect.c

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17803>
This commit is contained in:
Yonggang Luo 2022-08-07 15:20:43 +08:00 • committed by Marge Bot
parent e51fa10f53
commit e8ac138c83
1 changed files with 32 additions and 6 deletions
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38
src/util/u_cpu_detect.c
View file

@ -793,13 +793,39 @@ util_cpu_detect_once(void)
if (cacheline > 0)
util_cpu_caps.cacheline = cacheline;
}
}
#endif /* PIPE_ARCH_X86 || PIPE_ARCH_X86_64 */
if (!util_cpu_caps.has_sse) {
util_cpu_caps.has_sse2 = 0;
util_cpu_caps.has_sse3 = 0;
util_cpu_caps.has_ssse3 = 0;
util_cpu_caps.has_sse4_1 = 0;
}
#if defined(PIPE_ARCH_X86) || defined(PIPE_ARCH_X86_64)
if (!util_cpu_caps.has_sse) {
util_cpu_caps.has_sse2 = 0;
}
if (!util_cpu_caps.has_sse2) {
util_cpu_caps.has_sse3 = 0;
}
if (!util_cpu_caps.has_sse3) {
util_cpu_caps.has_ssse3 = 0;
util_cpu_caps.has_sse4_1 = 0;
}
if (!util_cpu_caps.has_sse4_1) {
util_cpu_caps.has_sse4_2 = 0;
util_cpu_caps.has_avx = 0;
}
if (!util_cpu_caps.has_avx) {
util_cpu_caps.has_avx2 = 0;
util_cpu_caps.has_f16c = 0;
util_cpu_caps.has_fma = 0;
/* avx512 are cleared */
util_cpu_caps.has_avx512f = 0;
util_cpu_caps.has_avx512dq = 0;
util_cpu_caps.has_avx512ifma = 0;
util_cpu_caps.has_avx512pf = 0;
util_cpu_caps.has_avx512er = 0;
util_cpu_caps.has_avx512cd = 0;
util_cpu_caps.has_avx512bw = 0;
util_cpu_caps.has_avx512vl = 0;
util_cpu_caps.has_avx512vbmi = 0;
}
#endif /* PIPE_ARCH_X86 || PIPE_ARCH_X86_64 */