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intel/brw: Avoid a silly add with zero in assign_curb_setup

Browse source 
No shader-db changes.

fossil-db:

DG2
Totals:
Instrs: 161008251 -> 161004452 (-0.00%)
Cycles: 13894249509 -> 13893050101 (-0.01%); split: -0.01%, +0.00%

Totals from 3804 (0.58% of 652145) affected shaders:
Instrs: 2232984 -> 2229185 (-0.17%)
Cycles: 7124966553 -> 7123767145 (-0.02%); split: -0.02%, +0.00%

No fossil-db changes on any other platform.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27552>
This commit is contained in:
Ian Romanick 2024-01-26 12:25:41 -08:00 • committed by Marge Bot
parent d9674cbe7d
commit e87881f616
1 changed files with 11 additions and 2 deletions
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13
src/intel/compiler/brw_fs.cpp
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@ -1270,8 +1270,17 @@ fs_visitor::assign_curb_setup()
assert(num_regs > 0);
num_regs = 1 << util_logbase2(num_regs);
fs_reg addr = ubld.vgrf(BRW_REGISTER_TYPE_UD);
ubld.ADD(addr, base_addr, brw_imm_ud(i * REG_SIZE));
fs_reg addr;
/* This pass occurs after all of the optimization passes, so don't
* emit an 'ADD addr, base_addr, 0' instruction.
*/
if (i != 0) {
addr = ubld.vgrf(BRW_REGISTER_TYPE_UD);
ubld.ADD(addr, base_addr, brw_imm_ud(i * REG_SIZE));
} else {
addr = base_addr;
}
fs_reg srcs[4] = {
brw_imm_ud(0), /* desc */