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i965/gen6/gs: implement GS_OPCODE_SVB_WRITE opcode
This opcode will be used when sending SVB WRITE messages to save transform feedback outputs into Streamed Vertex Buffers. Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com> Acked-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
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4 changed files with 63 additions and 0 deletions
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@ -1043,6 +1043,18 @@ enum opcode {
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* - dst is the GRF where PrimitiveID information will be moved.
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*/
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GS_OPCODE_SET_PRIMITIVE_ID,
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/**
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* Write transform feedback data to the SVB by sending a SVB WRITE message.
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* Used in gen6.
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*
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* - dst is the MRF register containing the message header.
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*
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* - src0 is the register where the vertex data is going to be copied from.
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*
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* - src1 is the destination register when write commit occurs.
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*/
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GS_OPCODE_SVB_WRITE,
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};
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enum brw_derivative_quality {
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@ -528,6 +528,8 @@ brw_instruction_name(enum opcode op)
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return "ff_sync";
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case GS_OPCODE_SET_PRIMITIVE_ID:
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return "set_primitive_id";
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case GS_OPCODE_SVB_WRITE:
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return "gs_svb_write";
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default:
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/* Yes, this leaks. It's in debug code, it should never occur, and if
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@ -220,6 +220,9 @@ public:
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enum brw_urb_write_flags urb_write_flags;
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bool header_present;
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unsigned sol_binding; /**< gen6: SOL binding table index */
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bool sol_final_write; /**< gen6: send commit message */
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bool is_send_from_grf();
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bool can_reswizzle(int dst_writemask, int swizzle, int swizzle_mask);
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void reswizzle(int dst_writemask, int swizzle);
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@ -654,6 +657,10 @@ private:
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struct brw_reg src1);
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void generate_gs_set_vertex_count(struct brw_reg dst,
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struct brw_reg src);
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void generate_gs_svb_write(vec4_instruction *inst,
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struct brw_reg dst,
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struct brw_reg src0,
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struct brw_reg src1);
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void generate_gs_set_dword_2(struct brw_reg dst, struct brw_reg src);
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void generate_gs_prepare_channel_masks(struct brw_reg dst);
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void generate_gs_set_channel_masks(struct brw_reg dst, struct brw_reg src);
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@ -573,6 +573,44 @@ vec4_generator::generate_gs_set_vertex_count(struct brw_reg dst,
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brw_pop_insn_state(p);
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}
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void
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vec4_generator::generate_gs_svb_write(vec4_instruction *inst,
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struct brw_reg dst,
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struct brw_reg src0,
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struct brw_reg src1)
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{
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int binding = inst->sol_binding;
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bool final_write = inst->sol_final_write;
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brw_push_insn_state(p);
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/* Copy Vertex data into M0.x */
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brw_MOV(p, stride(dst, 4, 4, 1),
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stride(retype(src0, BRW_REGISTER_TYPE_UD), 4, 4, 1));
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/* Send SVB Write */
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brw_svb_write(p,
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final_write ? src1 : brw_null_reg(), /* dest == src1 */
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1, /* msg_reg_nr */
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dst, /* src0 == previous dst */
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SURF_INDEX_GEN6_SOL_BINDING(binding), /* binding_table_index */
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final_write); /* send_commit_msg */
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/* Finally, wait for the write commit to occur so that we can proceed to
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* other things safely.
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*
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* From the Sandybridge PRM, Volume 4, Part 1, Section 3.3:
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*
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* The write commit does not modify the destination register, but
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* merely clears the dependency associated with the destination
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* register. Thus, a simple “mov” instruction using the register as a
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* source is sufficient to wait for the write commit to occur.
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*/
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if (final_write) {
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brw_MOV(p, src1, src1);
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}
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brw_pop_insn_state(p);
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}
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void
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vec4_generator::generate_gs_set_dword_2(struct brw_reg dst, struct brw_reg src)
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{
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@ -1347,6 +1385,10 @@ vec4_generator::generate_code(const cfg_t *cfg)
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generate_gs_urb_write_allocate(inst);
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break;
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case GS_OPCODE_SVB_WRITE:
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generate_gs_svb_write(inst, dst, src[0], src[1]);
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break;
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case GS_OPCODE_THREAD_END:
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generate_gs_thread_end(inst);
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break;
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