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i965: Account for poor address calculations in Haswell CS scratch size.
Curro figured this out by investigating the simulator. Apparently
there's also a workaround in the Windows driver. I'm not sure it's
actually documented anywhere.
We were underallocating the scratch buffer by a factor of 128/70.
v2: Rename threads_per_subslice to scratch_ids_per_subslice
(suggested by Jordan Justen).
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
(cherry picked from commit a7d029d3df)
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1 changed files with 20 additions and 1 deletions
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@ -150,9 +150,28 @@ brw_codegen_cs_prog(struct brw_context *brw,
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if (prog_data.base.total_scratch) {
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const unsigned subslices = MAX2(brw->intelScreen->subslice_total, 1);
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/* WaCSScratchSize:hsw
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*
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* Haswell's scratch space address calculation appears to be sparse
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* rather than tightly packed. The Thread ID has bits indicating
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* which subslice, EU within a subslice, and thread within an EU
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* it is. There's a maximum of two slices and two subslices, so these
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* can be stored with a single bit. Even though there are only 10 EUs
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* per subslice, this is stored in 4 bits, so there's an effective
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* maximum value of 16 EUs. Similarly, although there are only 7
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* threads per EU, this is stored in a 3 bit number, giving an effective
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* maximum value of 8 threads per EU.
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*
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* This means that we need to use 16 * 8 instead of 10 * 7 for the
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* number of threads per subslice.
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*/
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const unsigned scratch_ids_per_subslice =
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brw->is_haswell ? 16 * 8 : brw->max_cs_threads;
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brw_get_scratch_bo(brw, &brw->cs.base.scratch_bo,
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prog_data.base.total_scratch *
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brw->max_cs_threads * subslices);
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scratch_ids_per_subslice * subslices);
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}
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if (unlikely(INTEL_DEBUG & DEBUG_CS))
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