pan/midgard: Use more aggressive writeout criteria

We loosen the requirement of "no dependencies" to simply be "no
non-pipelined dependencies", so we check for what could be pipelined.

total bundles in shared programs: 2176 -> 2156 (-0.92%)
bundles in affected programs: 779 -> 759 (-2.57%)
helped: 20
HURT: 0
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 0.33% max: 20.00% x̄: 6.47% x̃: 2.78%
95% mean confidence interval for bundles value: -1.00 -1.00
95% mean confidence interval for bundles %-change: -9.44% -3.50%
Bundles are helped.

total quadwords in shared programs: 3605 -> 3585 (-0.55%)
quadwords in affected programs: 1391 -> 1371 (-1.44%)
helped: 20
HURT: 0
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 0.19% max: 14.29% x̄: 3.84% x̃: 1.64%
95% mean confidence interval for quadwords value: -1.00 -1.00
95% mean confidence interval for quadwords %-change: -5.73% -1.94%
Quadwords are helped.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
This commit is contained in:
Alyssa Rosenzweig 2019-07-26 08:30:22 -07:00
parent c7fc5f3567
commit e823d33e77

View file

@ -122,14 +122,14 @@ midgard_has_hazard(
*
* - All components of r0 are written in the bundle
* - No components of r0 are written in VLUT
* - Dependencies of r0 are not written in the bundle
* - Non-pipelined dependencies of r0 are not written in the bundle
*
* This function checks if these requirements are satisfied given the content
* of a scheduled bundle.
*/
static bool
can_writeout_fragment(midgard_instruction **bundle, unsigned count, unsigned node_count)
can_writeout_fragment(compiler_context *ctx, midgard_instruction **bundle, unsigned count, unsigned node_count)
{
/* First scan for which components of r0 are written out. Initially
* none are written */
@ -148,10 +148,20 @@ can_writeout_fragment(midgard_instruction **bundle, unsigned count, unsigned nod
/* Record written out mask */
r0_written_mask |= ins->mask;
/* Record dependencies */
/* Record dependencies, but only if they won't become pipeline
* registers. We know we can't be live after this, because
* we're writeout at the very end of the shader. So check if
* they were written before us. */
unsigned src0 = ins->ssa_args.src0;
unsigned src1 = ins->ssa_args.src1;
if (!mir_is_written_before(ctx, bundle[0], src0))
src0 = -1;
if (!mir_is_written_before(ctx, bundle[0], src1))
src1 = -1;
if ((src0 > 0) && (src0 < node_count))
BITSET_SET(dependencies, src0);
@ -452,7 +462,7 @@ schedule_bundle(compiler_context *ctx, midgard_block *block, midgard_instruction
unsigned node_count = ctx->func->impl->ssa_alloc + ctx->func->impl->reg_alloc;
if (ains->writeout && !can_writeout_fragment(scheduled, index, node_count)) {
if (ains->writeout && !can_writeout_fragment(ctx, scheduled, index, node_count)) {
/* We only work on full moves
* at the beginning. We could
* probably do better */