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i965: store workaround_bo offset

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This offset store the location where we read/write into the
workaround_bo. It will allow to select a different address later,
leaving the beginning of the buffer to some other use.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3203>
This commit is contained in:
Lionel Landwerlin 2020-02-21 18:12:50 +02:00 • committed by Marge Bot
parent 07781f0afe
commit e81de67d85
4 changed files with 13 additions and 5 deletions
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1
src/mesa/drivers/dri/i965/brw_context.h
View file

@ -725,6 +725,7 @@ struct brw_context
/** BO for post-sync nonzero writes for gen6 workaround. */
struct brw_bo *workaround_bo;
uint32_t workaround_bo_offset;
uint8_t pipe_controls_since_last_cs_stall;
/**

15
src/mesa/drivers/dri/i965/brw_pipe_control.c
View file

@ -124,7 +124,8 @@ gen7_emit_vs_workaround_flush(struct brw_context *brw)
brw_emit_pipe_control_write(brw,
PIPE_CONTROL_WRITE_IMMEDIATE
| PIPE_CONTROL_DEPTH_STALL,
brw->workaround_bo, 0, 0);
brw->workaround_bo,
brw->workaround_bo_offset, 0);
}
/**
@ -192,7 +193,8 @@ gen7_emit_cs_stall_flush(struct brw_context *brw)
brw_emit_pipe_control_write(brw,
PIPE_CONTROL_CS_STALL
| PIPE_CONTROL_WRITE_IMMEDIATE,
brw->workaround_bo, 0, 0);
brw->workaround_bo,
brw->workaround_bo_offset, 0);
}
/**
@ -240,7 +242,8 @@ brw_emit_post_sync_nonzero_flush(struct brw_context *brw)
PIPE_CONTROL_STALL_AT_SCOREBOARD);
brw_emit_pipe_control_write(brw, PIPE_CONTROL_WRITE_IMMEDIATE,
brw->workaround_bo, 0, 0);
brw->workaround_bo,
brw->workaround_bo_offset, 0);
}
/*
@ -298,7 +301,8 @@ brw_emit_end_of_pipe_sync(struct brw_context *brw, uint32_t flags)
brw_emit_pipe_control_write(brw,
flags | PIPE_CONTROL_CS_STALL |
PIPE_CONTROL_WRITE_IMMEDIATE,
brw->workaround_bo, 0, 0);
brw->workaround_bo,
brw->workaround_bo_offset, 0);
if (devinfo->is_haswell) {
/* Haswell needs addition work-arounds:
@ -335,7 +339,7 @@ brw_emit_end_of_pipe_sync(struct brw_context *brw, uint32_t flags)
* 3DPRIMITIVE when needed anyway.
*/
brw_load_register_mem(brw, GEN7_3DPRIM_START_INSTANCE,
brw->workaround_bo, 0);
brw->workaround_bo, brw->workaround_bo_offset);
}
} else {
/* On gen4-5, a regular pipe control seems to suffice. */
@ -414,6 +418,7 @@ brw_init_pipe_control(struct brw_context *brw,
if (brw->workaround_bo == NULL)
return -ENOMEM;
brw->workaround_bo_offset = 0;
brw->pipe_controls_since_last_cs_stall = 0;
return 0;

1
src/mesa/drivers/dri/i965/genX_blorp_exec.c
View file

@ -239,6 +239,7 @@ blorp_get_workaround_address(struct blorp_batch *batch)
return (struct blorp_address) {
.buffer = brw->workaround_bo,
.offset = brw->workaround_bo_offset,
};
}

1
src/mesa/drivers/dri/i965/genX_pipe_control.c
View file

@ -147,6 +147,7 @@ genX(emit_raw_pipe_control)(struct brw_context *brw, uint32_t flags,
post_sync_flags |= PIPE_CONTROL_WRITE_IMMEDIATE;
non_lri_post_sync_flags |= PIPE_CONTROL_WRITE_IMMEDIATE;
bo = brw->workaround_bo;
offset = brw->workaround_bo_offset;
}
}