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winsys/amdgpu: add addrlib - texture addressing and alignment calculator

Browse source 
This is an internal project that Catalyst uses and now open source will do
too.

v2: squashed these commits in:
    - winsys/amdgpu: fix warnings in addrlib
    - winsys/amdgpu: set PIPE_CONFIG and NUM_BANKS in tiling_flags
This commit is contained in:
Marek Olšák 2015-04-16 19:41:33 +02:00
parent 2eb067db0f
commit e7fc664b91
31 changed files with 22378 additions and 7 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
src/gallium/drivers/r300/r300_state.c
View file

@ -844,7 +844,7 @@ static void r300_tex_set_tiling_flags(struct r300_context *r300,
tex->tex.macrotile[level]) {
r300->rws->buffer_set_tiling(tex->buf, r300->cs,
tex->tex.microtile, tex->tex.macrotile[level],
0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0,
tex->tex.stride_in_bytes[0], false);
tex->surface_level = level;

2
src/gallium/drivers/r300/r300_texture.c
View file

@ -1063,7 +1063,7 @@ r300_texture_create_object(struct r300_screen *rscreen,
rws->buffer_set_tiling(tex->buf, NULL,
tex->tex.microtile, tex->tex.macrotile[0],
0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0,
tex->tex.stride_in_bytes[0], false);
return tex;

3
src/gallium/drivers/radeon/r600_texture.c
View file

@ -243,10 +243,11 @@ static boolean r600_texture_get_handle(struct pipe_screen* screen,
RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
surface->level[0].mode >= RADEON_SURF_MODE_2D ?
RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
surface->pipe_config,
surface->bankw, surface->bankh,
surface->tile_split,
surface->stencil_tile_split,
surface->mtilea,
surface->mtilea, surface->num_banks,
surface->level[0].pitch_bytes,
(surface->flags & RADEON_SURF_SCANOUT) != 0);

5
src/gallium/drivers/radeon/radeon_winsys.h
View file

@ -322,6 +322,8 @@ struct radeon_surf {
struct radeon_surf_level stencil_level[RADEON_SURF_MAX_LEVEL];
uint32_t tiling_index[RADEON_SURF_MAX_LEVEL];
uint32_t stencil_tiling_index[RADEON_SURF_MAX_LEVEL];
uint32_t pipe_config;
uint32_t num_banks;
};
struct radeon_winsys {
@ -446,10 +448,11 @@ struct radeon_winsys {
struct radeon_winsys_cs *rcs,
enum radeon_bo_layout microtile,
enum radeon_bo_layout macrotile,
unsigned pipe_config,
unsigned bankw, unsigned bankh,
unsigned tile_split,
unsigned stencil_tile_split,
unsigned mtilea,
unsigned mtilea, unsigned num_banks,
unsigned stride,
bool scanout);

7
src/gallium/winsys/amdgpu/drm/Makefile.am
View file

@ -3,7 +3,12 @@ include $(top_srcdir)/src/gallium/Automake.inc
AM_CFLAGS = \
$(GALLIUM_WINSYS_CFLAGS) \
$(AMDGPU_CFLAGS)
$(AMDGPU_CFLAGS) \
-I$(srcdir)/addrlib \
-I$(srcdir)/addrlib/core \
-I$(srcdir)/addrlib/inc/chip/r800 \
-I$(srcdir)/addrlib/r800/chip \
-DBRAHMA_BUILD=1
AM_CXXFLAGS = $(AM_CFLAGS)

23
src/gallium/winsys/amdgpu/drm/Makefile.sources
View file

@ -1,8 +1,31 @@
C_SOURCES := \
addrlib/addrinterface.cpp \
addrlib/addrinterface.h \
addrlib/addrtypes.h \
addrlib/core/addrcommon.h \
addrlib/core/addrelemlib.cpp \
addrlib/core/addrelemlib.h \
addrlib/core/addrlib.cpp \
addrlib/core/addrlib.h \
addrlib/core/addrobject.cpp \
addrlib/core/addrobject.h \
addrlib/inc/chip/r800/si_gb_reg.h \
addrlib/inc/lnx_common_defs.h \
addrlib/r800/chip/si_ci_merged_enum.h \
addrlib/r800/chip/si_ci_vi_merged_enum.h \
addrlib/r800/chip/si_enum.h \
addrlib/r800/ciaddrlib.cpp \
addrlib/r800/ciaddrlib.h \
addrlib/r800/egbaddrlib.cpp \
addrlib/r800/egbaddrlib.h \
addrlib/r800/siaddrlib.cpp \
addrlib/r800/siaddrlib.h \
amdgpu_bo.c \
amdgpu_bo.h \
amdgpu_cs.c \
amdgpu_cs.h \
amdgpu_id.h \
amdgpu_public.h \
amdgpu_surface.c \
amdgpu_winsys.c \
amdgpu_winsys.h

1008
src/gallium/winsys/amdgpu/drm/addrlib/addrinterface.cpp Normal file
View file

File diff suppressed because it is too large Load diff

2166
src/gallium/winsys/amdgpu/drm/addrlib/addrinterface.h Normal file
View file

File diff suppressed because it is too large Load diff

590
src/gallium/winsys/amdgpu/drm/addrlib/addrtypes.h Normal file
View file

@ -0,0 +1,590 @@
/*
* Copyright © 2014 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*/
/**
***************************************************************************************************
* @file addrtypes.h
* @brief Contains the helper function and constants
***************************************************************************************************
*/
#ifndef __ADDR_TYPES_H__
#define __ADDR_TYPES_H__
#if defined(__APPLE__) || defined(TCORE_BUILD)
// External definitions header maintained by Mac driver team (and TCORE team)
// Helps address compilation issues & reduces code covered by NDA
#include "addrExtDef.h"
#else
// Windows and/or Linux
#if !defined(VOID)
typedef void VOID;
#endif
#if !defined(FLOAT)
typedef float FLOAT;
#endif
#if !defined(CHAR)
typedef char CHAR;
#endif
#if !defined(INT)
typedef int INT;
#endif
#include <stdarg.h> // va_list...etc need this header
#endif // defined (__APPLE__)
/**
***************************************************************************************************
* Calling conventions
***************************************************************************************************
*/
#ifndef ADDR_CDECL
#if defined(__GNUC__)
#define ADDR_CDECL __attribute__((cdecl))
#else
#define ADDR_CDECL __cdecl
#endif
#endif
#ifndef ADDR_STDCALL
#if defined(__GNUC__)
#if defined(__AMD64__)
#define ADDR_STDCALL
#else
#define ADDR_STDCALL __attribute__((stdcall))
#endif
#else
#define ADDR_STDCALL __stdcall
#endif
#endif
#ifndef ADDR_FASTCALL
#if defined(__GNUC__)
#define ADDR_FASTCALL __attribute__((regparm(0)))
#else
#define ADDR_FASTCALL __fastcall
#endif
#endif
#ifndef GC_CDECL
#define GC_CDECL ADDR_CDECL
#endif
#ifndef GC_STDCALL
#define GC_STDCALL ADDR_STDCALL
#endif
#ifndef GC_FASTCALL
#define GC_FASTCALL ADDR_FASTCALL
#endif
#if defined(__GNUC__)
#define ADDR_INLINE static inline // inline needs to be static to link
#else
// win32, win64, other platforms
#define ADDR_INLINE __inline
#endif // #if defined(__GNUC__)
#define ADDR_API ADDR_FASTCALL //default call convention is fast call
/**
***************************************************************************************************
* Global defines used by other modules
***************************************************************************************************
*/
#if !defined(TILEINDEX_INVALID)
#define TILEINDEX_INVALID -1
#endif
#if !defined(TILEINDEX_LINEAR_GENERAL)
#define TILEINDEX_LINEAR_GENERAL -2
#endif
#if !defined(TILEINDEX_LINEAR_ALIGNED)
#define TILEINDEX_LINEAR_ALIGNED 8
#endif
/**
***************************************************************************************************
* Return codes
***************************************************************************************************
*/
typedef enum _ADDR_E_RETURNCODE
{
// General Return
ADDR_OK = 0,
ADDR_ERROR = 1,
// Specific Errors
ADDR_OUTOFMEMORY,
ADDR_INVALIDPARAMS,
ADDR_NOTSUPPORTED,
ADDR_NOTIMPLEMENTED,
ADDR_PARAMSIZEMISMATCH,
ADDR_INVALIDGBREGVALUES,
} ADDR_E_RETURNCODE;
/**
***************************************************************************************************
* @brief
* Neutral enums that define tile modes for all H/W
* @note
* R600/R800 tiling mode can be cast to hw enums directly but never cast into HW enum from
* ADDR_TM_2D_TILED_XTHICK
*
***************************************************************************************************
*/
typedef enum _AddrTileMode
{
ADDR_TM_LINEAR_GENERAL = 0, ///< Least restrictions, pitch: multiple of 8 if not buffer
ADDR_TM_LINEAR_ALIGNED = 1, ///< Requests pitch or slice to be multiple of 64 pixels
ADDR_TM_1D_TILED_THIN1 = 2, ///< Linear array of 8x8 tiles
ADDR_TM_1D_TILED_THICK = 3, ///< Linear array of 8x8x4 tiles
ADDR_TM_2D_TILED_THIN1 = 4, ///< A set of macro tiles consist of 8x8 tiles
ADDR_TM_2D_TILED_THIN2 = 5, ///< 600 HWL only, macro tile ratio is 1:4
ADDR_TM_2D_TILED_THIN4 = 6, ///< 600 HWL only, macro tile ratio is 1:16
ADDR_TM_2D_TILED_THICK = 7, ///< A set of macro tiles consist of 8x8x4 tiles
ADDR_TM_2B_TILED_THIN1 = 8, ///< 600 HWL only, with bank swap
ADDR_TM_2B_TILED_THIN2 = 9, ///< 600 HWL only, with bank swap and ratio is 1:4
ADDR_TM_2B_TILED_THIN4 = 10, ///< 600 HWL only, with bank swap and ratio is 1:16
ADDR_TM_2B_TILED_THICK = 11, ///< 600 HWL only, with bank swap, consists of 8x8x4 tiles
ADDR_TM_3D_TILED_THIN1 = 12, ///< Macro tiling w/ pipe rotation between slices
ADDR_TM_3D_TILED_THICK = 13, ///< Macro tiling w/ pipe rotation bwtween slices, thick
ADDR_TM_3B_TILED_THIN1 = 14, ///< 600 HWL only, with bank swap
ADDR_TM_3B_TILED_THICK = 15, ///< 600 HWL only, with bank swap, thick
ADDR_TM_2D_TILED_XTHICK = 16, ///< Tile is 8x8x8, valid from NI
ADDR_TM_3D_TILED_XTHICK = 17, ///< Tile is 8x8x8, valid from NI
ADDR_TM_POWER_SAVE = 18, ///< Power save mode, only used by KMD on NI
ADDR_TM_PRT_TILED_THIN1 = 19, ///< No bank/pipe rotation or hashing beyond macrotile size
ADDR_TM_PRT_2D_TILED_THIN1 = 20, ///< Same as 2D_TILED_THIN1, PRT only
ADDR_TM_PRT_3D_TILED_THIN1 = 21, ///< Same as 3D_TILED_THIN1, PRT only
ADDR_TM_PRT_TILED_THICK = 22, ///< No bank/pipe rotation or hashing beyond macrotile size
ADDR_TM_PRT_2D_TILED_THICK = 23, ///< Same as 2D_TILED_THICK, PRT only
ADDR_TM_PRT_3D_TILED_THICK = 24, ///< Same as 3D_TILED_THICK, PRT only
ADDR_TM_COUNT = 25, ///< Must be the value of the last tile mode
} AddrTileMode;
/**
***************************************************************************************************
* AddrFormat
*
* @brief
* Neutral enum for SurfaceFormat
*
***************************************************************************************************
*/
typedef enum _AddrFormat {
ADDR_FMT_INVALID = 0x00000000,
ADDR_FMT_8 = 0x00000001,
ADDR_FMT_4_4 = 0x00000002,
ADDR_FMT_3_3_2 = 0x00000003,
ADDR_FMT_RESERVED_4 = 0x00000004,
ADDR_FMT_16 = 0x00000005,
ADDR_FMT_16_FLOAT = 0x00000006,
ADDR_FMT_8_8 = 0x00000007,
ADDR_FMT_5_6_5 = 0x00000008,
ADDR_FMT_6_5_5 = 0x00000009,
ADDR_FMT_1_5_5_5 = 0x0000000a,
ADDR_FMT_4_4_4_4 = 0x0000000b,
ADDR_FMT_5_5_5_1 = 0x0000000c,
ADDR_FMT_32 = 0x0000000d,
ADDR_FMT_32_FLOAT = 0x0000000e,
ADDR_FMT_16_16 = 0x0000000f,
ADDR_FMT_16_16_FLOAT = 0x00000010,
ADDR_FMT_8_24 = 0x00000011,
ADDR_FMT_8_24_FLOAT = 0x00000012,
ADDR_FMT_24_8 = 0x00000013,
ADDR_FMT_24_8_FLOAT = 0x00000014,
ADDR_FMT_10_11_11 = 0x00000015,
ADDR_FMT_10_11_11_FLOAT = 0x00000016,
ADDR_FMT_11_11_10 = 0x00000017,
ADDR_FMT_11_11_10_FLOAT = 0x00000018,
ADDR_FMT_2_10_10_10 = 0x00000019,
ADDR_FMT_8_8_8_8 = 0x0000001a,
ADDR_FMT_10_10_10_2 = 0x0000001b,
ADDR_FMT_X24_8_32_FLOAT = 0x0000001c,
ADDR_FMT_32_32 = 0x0000001d,
ADDR_FMT_32_32_FLOAT = 0x0000001e,
ADDR_FMT_16_16_16_16 = 0x0000001f,
ADDR_FMT_16_16_16_16_FLOAT = 0x00000020,
ADDR_FMT_RESERVED_33 = 0x00000021,
ADDR_FMT_32_32_32_32 = 0x00000022,
ADDR_FMT_32_32_32_32_FLOAT = 0x00000023,
ADDR_FMT_RESERVED_36 = 0x00000024,
ADDR_FMT_1 = 0x00000025,
ADDR_FMT_1_REVERSED = 0x00000026,
ADDR_FMT_GB_GR = 0x00000027,
ADDR_FMT_BG_RG = 0x00000028,
ADDR_FMT_32_AS_8 = 0x00000029,
ADDR_FMT_32_AS_8_8 = 0x0000002a,
ADDR_FMT_5_9_9_9_SHAREDEXP = 0x0000002b,
ADDR_FMT_8_8_8 = 0x0000002c,
ADDR_FMT_16_16_16 = 0x0000002d,
ADDR_FMT_16_16_16_FLOAT = 0x0000002e,
ADDR_FMT_32_32_32 = 0x0000002f,
ADDR_FMT_32_32_32_FLOAT = 0x00000030,
ADDR_FMT_BC1 = 0x00000031,
ADDR_FMT_BC2 = 0x00000032,
ADDR_FMT_BC3 = 0x00000033,
ADDR_FMT_BC4 = 0x00000034,
ADDR_FMT_BC5 = 0x00000035,
ADDR_FMT_BC6 = 0x00000036,
ADDR_FMT_BC7 = 0x00000037,
ADDR_FMT_32_AS_32_32_32_32 = 0x00000038,
ADDR_FMT_APC3 = 0x00000039,
ADDR_FMT_APC4 = 0x0000003a,
ADDR_FMT_APC5 = 0x0000003b,
ADDR_FMT_APC6 = 0x0000003c,
ADDR_FMT_APC7 = 0x0000003d,
ADDR_FMT_CTX1 = 0x0000003e,
ADDR_FMT_RESERVED_63 = 0x0000003f,
} AddrFormat;
/**
***************************************************************************************************
* AddrDepthFormat
*
* @brief
* Neutral enum for addrFlt32ToDepthPixel
*
***************************************************************************************************
*/
typedef enum _AddrDepthFormat
{
ADDR_DEPTH_INVALID = 0x00000000,
ADDR_DEPTH_16 = 0x00000001,
ADDR_DEPTH_X8_24 = 0x00000002,
ADDR_DEPTH_8_24 = 0x00000003,
ADDR_DEPTH_X8_24_FLOAT = 0x00000004,
ADDR_DEPTH_8_24_FLOAT = 0x00000005,
ADDR_DEPTH_32_FLOAT = 0x00000006,
ADDR_DEPTH_X24_8_32_FLOAT = 0x00000007,
} AddrDepthFormat;
/**
***************************************************************************************************
* AddrColorFormat
*
* @brief
* Neutral enum for ColorFormat
*
***************************************************************************************************
*/
typedef enum _AddrColorFormat
{
ADDR_COLOR_INVALID = 0x00000000,
ADDR_COLOR_8 = 0x00000001,
ADDR_COLOR_4_4 = 0x00000002,
ADDR_COLOR_3_3_2 = 0x00000003,
ADDR_COLOR_RESERVED_4 = 0x00000004,
ADDR_COLOR_16 = 0x00000005,
ADDR_COLOR_16_FLOAT = 0x00000006,
ADDR_COLOR_8_8 = 0x00000007,
ADDR_COLOR_5_6_5 = 0x00000008,
ADDR_COLOR_6_5_5 = 0x00000009,
ADDR_COLOR_1_5_5_5 = 0x0000000a,
ADDR_COLOR_4_4_4_4 = 0x0000000b,
ADDR_COLOR_5_5_5_1 = 0x0000000c,
ADDR_COLOR_32 = 0x0000000d,
ADDR_COLOR_32_FLOAT = 0x0000000e,
ADDR_COLOR_16_16 = 0x0000000f,
ADDR_COLOR_16_16_FLOAT = 0x00000010,
ADDR_COLOR_8_24 = 0x00000011,
ADDR_COLOR_8_24_FLOAT = 0x00000012,
ADDR_COLOR_24_8 = 0x00000013,
ADDR_COLOR_24_8_FLOAT = 0x00000014,
ADDR_COLOR_10_11_11 = 0x00000015,
ADDR_COLOR_10_11_11_FLOAT = 0x00000016,
ADDR_COLOR_11_11_10 = 0x00000017,
ADDR_COLOR_11_11_10_FLOAT = 0x00000018,
ADDR_COLOR_2_10_10_10 = 0x00000019,
ADDR_COLOR_8_8_8_8 = 0x0000001a,
ADDR_COLOR_10_10_10_2 = 0x0000001b,
ADDR_COLOR_X24_8_32_FLOAT = 0x0000001c,
ADDR_COLOR_32_32 = 0x0000001d,
ADDR_COLOR_32_32_FLOAT = 0x0000001e,
ADDR_COLOR_16_16_16_16 = 0x0000001f,
ADDR_COLOR_16_16_16_16_FLOAT = 0x00000020,
ADDR_COLOR_RESERVED_33 = 0x00000021,
ADDR_COLOR_32_32_32_32 = 0x00000022,
ADDR_COLOR_32_32_32_32_FLOAT = 0x00000023,
} AddrColorFormat;
/**
***************************************************************************************************
* AddrSurfaceNumber
*
* @brief
* Neutral enum for SurfaceNumber
*
***************************************************************************************************
*/
typedef enum _AddrSurfaceNumber {
ADDR_NUMBER_UNORM = 0x00000000,
ADDR_NUMBER_SNORM = 0x00000001,
ADDR_NUMBER_USCALED = 0x00000002,
ADDR_NUMBER_SSCALED = 0x00000003,
ADDR_NUMBER_UINT = 0x00000004,
ADDR_NUMBER_SINT = 0x00000005,
ADDR_NUMBER_SRGB = 0x00000006,
ADDR_NUMBER_FLOAT = 0x00000007,
} AddrSurfaceNumber;
/**
***************************************************************************************************
* AddrSurfaceSwap
*
* @brief
* Neutral enum for SurfaceSwap
*
***************************************************************************************************
*/
typedef enum _AddrSurfaceSwap {
ADDR_SWAP_STD = 0x00000000,
ADDR_SWAP_ALT = 0x00000001,
ADDR_SWAP_STD_REV = 0x00000002,
ADDR_SWAP_ALT_REV = 0x00000003,
} AddrSurfaceSwap;
/**
***************************************************************************************************
* AddrHtileBlockSize
*
* @brief
* Size of HTILE blocks, valid values are 4 or 8 for now
***************************************************************************************************
*/
typedef enum _AddrHtileBlockSize
{
ADDR_HTILE_BLOCKSIZE_4 = 4,
ADDR_HTILE_BLOCKSIZE_8 = 8,
} AddrHtileBlockSize;
/**
***************************************************************************************************
* AddrPipeCfg
*
* @brief
* The pipe configuration field specifies both the number of pipes and
* how pipes are interleaved on the surface.
* The expression of number of pipes, the shader engine tile size, and packer tile size
* is encoded in a PIPE_CONFIG register field.
* In general the number of pipes usually matches the number of memory channels of the
* hardware configuration.
* For hw configurations w/ non-pow2 memory number of memory channels, it usually matches
* the number of ROP units(? TODO: which registers??)
* The enum value = hw enum + 1 which is to reserve 0 for requesting default.
***************************************************************************************************
*/
typedef enum _AddrPipeCfg
{
ADDR_PIPECFG_INVALID = 0,
ADDR_PIPECFG_P2 = 1, /// 2 pipes,
ADDR_PIPECFG_P4_8x16 = 5, /// 4 pipes,
ADDR_PIPECFG_P4_16x16 = 6,
ADDR_PIPECFG_P4_16x32 = 7,
ADDR_PIPECFG_P4_32x32 = 8,
ADDR_PIPECFG_P8_16x16_8x16 = 9, /// 8 pipes
ADDR_PIPECFG_P8_16x32_8x16 = 10,
ADDR_PIPECFG_P8_32x32_8x16 = 11,
ADDR_PIPECFG_P8_16x32_16x16 = 12,
ADDR_PIPECFG_P8_32x32_16x16 = 13,
ADDR_PIPECFG_P8_32x32_16x32 = 14,
ADDR_PIPECFG_P8_32x64_32x32 = 15,
ADDR_PIPECFG_P16_32x32_8x16 = 17, /// 16 pipes
ADDR_PIPECFG_P16_32x32_16x16 = 18,
ADDR_PIPECFG_MAX = 19,
} AddrPipeCfg;
/**
***************************************************************************************************
* AddrTileType
*
* @brief
* Neutral enums that specifies micro tile type (MICRO_TILE_MODE)
***************************************************************************************************
*/
typedef enum _AddrTileType
{
ADDR_DISPLAYABLE = 0, ///< Displayable tiling
ADDR_NON_DISPLAYABLE = 1, ///< Non-displayable tiling, a.k.a thin micro tiling
ADDR_DEPTH_SAMPLE_ORDER = 2, ///< Same as non-displayable plus depth-sample-order
ADDR_ROTATED = 3, ///< Rotated displayable tiling
ADDR_THICK = 4, ///< Thick micro-tiling, only valid for THICK and XTHICK
} AddrTileType;
///////////////////////////////////////////////////////////////////////////////////////////////////
//
// Type definitions: short system-independent names for address library types
//
///////////////////////////////////////////////////////////////////////////////////////////////////
#if !defined(__APPLE__)
#ifndef BOOL_32 // no bool type in C
/// @brief Boolean type, since none is defined in C
/// @ingroup type
#define BOOL_32 int
#endif
#ifndef INT_32
#define INT_32 int
#endif
#ifndef UINT_32
#define UINT_32 unsigned int
#endif
#ifndef INT_16
#define INT_16 short
#endif
#ifndef UINT_16
#define UINT_16 unsigned short
#endif
#ifndef INT_8
#define INT_8 char
#endif
#ifndef UINT_8
#define UINT_8 unsigned char
#endif
#ifndef NULL
#define NULL 0
#endif
#ifndef TRUE
#define TRUE 1
#endif
#ifndef FALSE
#define FALSE 0
#endif
//
// 64-bit integer types depend on the compiler
//
#if defined( __GNUC__ ) || defined( __WATCOMC__ )
#define INT_64 long long
#define UINT_64 unsigned long long
#elif defined( _WIN32 )
#define INT_64 __int64
#define UINT_64 unsigned __int64
#else
#error Unsupported compiler and/or operating system for 64-bit integers
/// @brief 64-bit signed integer type (compiler dependent)
/// @ingroup type
///
/// The addrlib defines a 64-bit signed integer type for either
/// Gnu/Watcom compilers (which use the first syntax) or for
/// the Windows VCC compiler (which uses the second syntax).
#define INT_64 long long OR __int64
/// @brief 64-bit unsigned integer type (compiler dependent)
/// @ingroup type
///
/// The addrlib defines a 64-bit unsigned integer type for either
/// Gnu/Watcom compilers (which use the first syntax) or for
/// the Windows VCC compiler (which uses the second syntax).
///
#define UINT_64 unsigned long long OR unsigned __int64
#endif
#endif // #if !defined(__APPLE__)
// ADDR64X is used to print addresses in hex form on both Windows and Linux
//
#if defined( __GNUC__ ) || defined( __WATCOMC__ )
#define ADDR64X "llx"
#define ADDR64D "lld"
#elif defined( _WIN32 )
#define ADDR64X "I64x"
#define ADDR64D "I64d"
#else
#error Unsupported compiler and/or operating system for 64-bit integers
/// @brief Addrlib device address 64-bit printf tag (compiler dependent)
/// @ingroup type
///
/// This allows printf to display an ADDR_64 for either the Windows VCC compiler
/// (which used this value) or the Gnu/Watcom compilers (which use "llx".
/// An example of use is printf("addr 0x%"ADDR64X"\n", address);
///
#define ADDR64X "llx" OR "I64x"
#define ADDR64D "lld" OR "I64d"
#endif
/// @brief Union for storing a 32-bit float or 32-bit integer
/// @ingroup type
///
/// This union provides a simple way to convert between a 32-bit float
/// and a 32-bit integer. It also prevents the compiler from producing
/// code that alters NaN values when assiging or coying floats.
/// Therefore, all address library routines that pass or return 32-bit
/// floating point data do so by passing or returning a FLT_32.
///
typedef union {
INT_32 i;
UINT_32 u;
float f;
} ADDR_FLT_32;
///////////////////////////////////////////////////////////////////////////////////////////////////
//
// Macros for controlling linking and building on multiple systems
//
///////////////////////////////////////////////////////////////////////////////////////////////////
#if defined(_MSC_VER)
#if defined(va_copy)
#undef va_copy //redefine va_copy to support VC2013
#endif
#endif
#if !defined(va_copy)
#define va_copy(dst, src) \
((void) memcpy(&(dst), &(src), sizeof(va_list)))
#endif
#endif // __ADDR_TYPES_H__

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/*
* Copyright © 2014 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*/
/**
***************************************************************************************************
* @file addrcommon.h
* @brief Contains the helper function and constants
***************************************************************************************************
*/
#ifndef __ADDR_COMMON_H__
#define __ADDR_COMMON_H__
#include "addrinterface.h"
// ADDR_LNX_KERNEL_BUILD is for internal build
// Moved from addrinterface.h so __KERNEL__ is not needed any more
#if ADDR_LNX_KERNEL_BUILD // || (defined(__GNUC__) && defined(__KERNEL__))
#include "lnx_common_defs.h" // ported from cmmqs
#elif !defined(__APPLE__)
#include <stdlib.h>
#include <string.h>
#endif
///////////////////////////////////////////////////////////////////////////////////////////////////
// Common constants
///////////////////////////////////////////////////////////////////////////////////////////////////
static const UINT_32 MicroTileWidth = 8; ///< Micro tile width, for 1D and 2D tiling
static const UINT_32 MicroTileHeight = 8; ///< Micro tile height, for 1D and 2D tiling
static const UINT_32 ThickTileThickness = 4; ///< Micro tile thickness, for THICK modes
static const UINT_32 XThickTileThickness = 8; ///< Extra thick tiling thickness
static const UINT_32 PowerSaveTileBytes = 64; ///< Nuber of bytes per tile for power save 64
static const UINT_32 CmaskCacheBits = 1024; ///< Number of bits for CMASK cache
static const UINT_32 CmaskElemBits = 4; ///< Number of bits for CMASK element
static const UINT_32 HtileCacheBits = 16384; ///< Number of bits for HTILE cache 512*32
static const UINT_32 MicroTilePixels = MicroTileWidth * MicroTileHeight;
static const INT_32 TileIndexInvalid = TILEINDEX_INVALID;
static const INT_32 TileIndexLinearGeneral = TILEINDEX_LINEAR_GENERAL;
static const INT_32 TileIndexNoMacroIndex = -3;
///////////////////////////////////////////////////////////////////////////////////////////////////
// Common macros
///////////////////////////////////////////////////////////////////////////////////////////////////
#define BITS_PER_BYTE 8
#define BITS_TO_BYTES(x) ( ((x) + (BITS_PER_BYTE-1)) / BITS_PER_BYTE )
#define BYTES_TO_BITS(x) ( (x) * BITS_PER_BYTE )
/// Helper macros to select a single bit from an int (undefined later in section)
#define _BIT(v,b) (((v) >> (b) ) & 1)
/**
***************************************************************************************************
* @brief Enums to identify AddrLib type
***************************************************************************************************
*/
enum AddrLibClass
{
BASE_ADDRLIB = 0x0,
R600_ADDRLIB = 0x6,
R800_ADDRLIB = 0x8,
SI_ADDRLIB = 0xa,
CI_ADDRLIB = 0xb,
};
/**
***************************************************************************************************
* AddrChipFamily
*
* @brief
* Neutral enums that specifies chip family.
*
***************************************************************************************************
*/
enum AddrChipFamily
{
ADDR_CHIP_FAMILY_IVLD, ///< Invalid family
ADDR_CHIP_FAMILY_R6XX,
ADDR_CHIP_FAMILY_R7XX,
ADDR_CHIP_FAMILY_R8XX,
ADDR_CHIP_FAMILY_NI,
ADDR_CHIP_FAMILY_SI,
ADDR_CHIP_FAMILY_CI,
ADDR_CHIP_FAMILY_VI,
};
/**
***************************************************************************************************
* ADDR_CONFIG_FLAGS
*
* @brief
* This structure is used to set addr configuration flags.
***************************************************************************************************
*/
union ADDR_CONFIG_FLAGS
{
struct
{
/// Clients do not need to set these flags except forceLinearAligned.
/// There flags are set up by AddrLib inside thru AddrInitGlobalParamsFromRegister
UINT_32 optimalBankSwap : 1; ///< New bank tiling for RV770 only
UINT_32 noCubeMipSlicesPad : 1; ///< Disables faces padding for cubemap mipmaps
UINT_32 fillSizeFields : 1; ///< If clients fill size fields in all input and
/// output structure
UINT_32 ignoreTileInfo : 1; ///< Don't use tile info structure
UINT_32 useTileIndex : 1; ///< Make tileIndex field in input valid
UINT_32 useCombinedSwizzle : 1; ///< Use combined swizzle
UINT_32 checkLast2DLevel : 1; ///< Check the last 2D mip sub level
UINT_32 useHtileSliceAlign : 1; ///< Do htile single slice alignment
UINT_32 degradeBaseLevel : 1; ///< Degrade to 1D modes automatically for base level
UINT_32 allowLargeThickTile : 1; ///< Allow 64*thickness*bytesPerPixel > rowSize
UINT_32 reserved : 22; ///< Reserved bits for future use
};
UINT_32 value;
};
///////////////////////////////////////////////////////////////////////////////////////////////////
// Platform specific debug break defines
///////////////////////////////////////////////////////////////////////////////////////////////////
#if DEBUG
#if defined(__GNUC__)
#define ADDR_DBG_BREAK()
#elif defined(__APPLE__)
#define ADDR_DBG_BREAK() { IOPanic("");}
#else
#define ADDR_DBG_BREAK() { __debugbreak(); }
#endif
#else
#define ADDR_DBG_BREAK()
#endif
///////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////
// Debug assertions used in AddrLib
///////////////////////////////////////////////////////////////////////////////////////////////////
#if DEBUG
#define ADDR_ASSERT(__e) if ( !((__e) ? TRUE : FALSE)) { ADDR_DBG_BREAK(); }
#define ADDR_ASSERT_ALWAYS() ADDR_DBG_BREAK()
#define ADDR_UNHANDLED_CASE() ADDR_ASSERT(!"Unhandled case")
#define ADDR_NOT_IMPLEMENTED() ADDR_ASSERT(!"Not implemented");
#else //DEBUG
#define ADDR_ASSERT(__e)
#define ADDR_ASSERT_ALWAYS()
#define ADDR_UNHANDLED_CASE()
#define ADDR_NOT_IMPLEMENTED()
#endif //DEBUG
///////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////
// Debug print macro from legacy address library
///////////////////////////////////////////////////////////////////////////////////////////////////
#if DEBUG
#define ADDR_PRNT(a) AddrObject::DebugPrint a
/// @brief Macro for reporting informational messages
/// @ingroup util
///
/// This macro optionally prints an informational message to stdout.
/// The first parameter is a condition -- if it is true, nothing is done.
/// The second pararmeter MUST be a parenthesis-enclosed list of arguments,
/// starting with a string. This is passed to printf() or an equivalent
/// in order to format the informational message. For example,
/// ADDR_INFO(0, ("test %d",3) ); prints out "test 3".
///
#define ADDR_INFO(cond, a) \
{ if (!(cond)) { ADDR_PRNT(a); } }
/// @brief Macro for reporting error warning messages
/// @ingroup util
///
/// This macro optionally prints an error warning message to stdout,
/// followed by the file name and line number where the macro was called.
/// The first parameter is a condition -- if it is true, nothing is done.
/// The second pararmeter MUST be a parenthesis-enclosed list of arguments,
/// starting with a string. This is passed to printf() or an equivalent
/// in order to format the informational message. For example,
/// ADDR_WARN(0, ("test %d",3) ); prints out "test 3" followed by
/// a second line with the file name and line number.
///
#define ADDR_WARN(cond, a) \
{ if (!(cond)) \
{ ADDR_PRNT(a); \
ADDR_PRNT((" WARNING in file %s, line %d\n", __FILE__, __LINE__)); \
} }
/// @brief Macro for reporting fatal error conditions
/// @ingroup util
///
/// This macro optionally stops execution of the current routine
/// after printing an error warning message to stdout,
/// followed by the file name and line number where the macro was called.
/// The first parameter is a condition -- if it is true, nothing is done.
/// The second pararmeter MUST be a parenthesis-enclosed list of arguments,
/// starting with a string. This is passed to printf() or an equivalent
/// in order to format the informational message. For example,
/// ADDR_EXIT(0, ("test %d",3) ); prints out "test 3" followed by
/// a second line with the file name and line number, then stops execution.
///
#define ADDR_EXIT(cond, a) \
{ if (!(cond)) \
{ ADDR_PRNT(a); ADDR_DBG_BREAK();\
} }
#else // DEBUG
#define ADDRDPF 1 ? (void)0 : (void)
#define ADDR_PRNT(a)
#define ADDR_DBG_BREAK()
#define ADDR_INFO(cond, a)
#define ADDR_WARN(cond, a)
#define ADDR_EXIT(cond, a)
#endif // DEBUG
///////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////
// Misc helper functions
////////////////////////////////////////////////////////////////////////////////////////////////////
/**
***************************************************************************************************
* AddrXorReduce
*
* @brief
* Xor the right-side numberOfBits bits of x.
***************************************************************************************************
*/
static inline UINT_32 XorReduce(
UINT_32 x,
UINT_32 numberOfBits)
{
UINT_32 i;
UINT_32 result = x & 1;
for (i=1; i<numberOfBits; i++)
{
result ^= ((x>>i) & 1);
}
return result;
}
/**
***************************************************************************************************
* IsPow2
*
* @brief
* Check if the size (UINT_32) is pow 2
***************************************************************************************************
*/
static inline UINT_32 IsPow2(
UINT_32 dim) ///< [in] dimension of miplevel
{
ADDR_ASSERT(dim > 0);
return !(dim & (dim - 1));
}
/**
***************************************************************************************************
* IsPow2
*
* @brief
* Check if the size (UINT_64) is pow 2
***************************************************************************************************
*/
static inline UINT_64 IsPow2(
UINT_64 dim) ///< [in] dimension of miplevel
{
ADDR_ASSERT(dim > 0);
return !(dim & (dim - 1));
}
/**
***************************************************************************************************
* ByteAlign
*
* @brief
* Align UINT_32 "x" to "align" alignment, "align" should be power of 2
***************************************************************************************************
*/
static inline UINT_32 PowTwoAlign(
UINT_32 x,
UINT_32 align)
{
//
// Assert that x is a power of two.
//
ADDR_ASSERT(IsPow2(align));
return (x + (align - 1)) & (~(align - 1));
}
/**
***************************************************************************************************
* ByteAlign
*
* @brief
* Align UINT_64 "x" to "align" alignment, "align" should be power of 2
***************************************************************************************************
*/
static inline UINT_64 PowTwoAlign(
UINT_64 x,
UINT_64 align)
{
//
// Assert that x is a power of two.
//
ADDR_ASSERT(IsPow2(align));
return (x + (align - 1)) & (~(align - 1));
}
/**
***************************************************************************************************
* Min
*
* @brief
* Get the min value between two unsigned values
***************************************************************************************************
*/
static inline UINT_32 Min(
UINT_32 value1,
UINT_32 value2)
{
return ((value1 < (value2)) ? (value1) : value2);
}
/**
***************************************************************************************************
* Min
*
* @brief
* Get the min value between two signed values
***************************************************************************************************
*/
static inline INT_32 Min(
INT_32 value1,
INT_32 value2)
{
return ((value1 < (value2)) ? (value1) : value2);
}
/**
***************************************************************************************************
* Max
*
* @brief
* Get the max value between two unsigned values
***************************************************************************************************
*/
static inline UINT_32 Max(
UINT_32 value1,
UINT_32 value2)
{
return ((value1 > (value2)) ? (value1) : value2);
}
/**
***************************************************************************************************
* Max
*
* @brief
* Get the max value between two signed values
***************************************************************************************************
*/
static inline INT_32 Max(
INT_32 value1,
INT_32 value2)
{
return ((value1 > (value2)) ? (value1) : value2);
}
/**
***************************************************************************************************
* NextPow2
*
* @brief
* Compute the mipmap's next level dim size
***************************************************************************************************
*/
static inline UINT_32 NextPow2(
UINT_32 dim) ///< [in] dimension of miplevel
{
UINT_32 newDim;
newDim = 1;
if (dim > 0x7fffffff)
{
ADDR_ASSERT_ALWAYS();
newDim = 0x80000000;
}
else
{
while (newDim < dim)
{
newDim <<= 1;
}
}
return newDim;
}
/**
***************************************************************************************************
* Log2
*
* @brief
* Compute log of base 2
***************************************************************************************************
*/
static inline UINT_32 Log2(
UINT_32 x) ///< [in] the value should calculate log based 2
{
UINT_32 y;
//
// Assert that x is a power of two.
//
ADDR_ASSERT(IsPow2(x));
y = 0;
while (x > 1)
{
x >>= 1;
y++;
}
return y;
}
/**
***************************************************************************************************
* QLog2
*
* @brief
* Compute log of base 2 quickly (<= 16)
***************************************************************************************************
*/
static inline UINT_32 QLog2(
UINT_32 x) ///< [in] the value should calculate log based 2
{
ADDR_ASSERT(x <= 16);
UINT_32 y = 0;
switch (x)
{
case 1:
y = 0;
break;
case 2:
y = 1;
break;
case 4:
y = 2;
break;
case 8:
y = 3;
break;
case 16:
y = 4;
break;
default:
ADDR_ASSERT_ALWAYS();
}
return y;
}
/**
***************************************************************************************************
* SafeAssign
*
* @brief
* NULL pointer safe assignment
***************************************************************************************************
*/
static inline VOID SafeAssign(
UINT_32* pLVal, ///< [in] Pointer to left val
UINT_32 rVal) ///< [in] Right value
{
if (pLVal)
{
*pLVal = rVal;
}
}
/**
***************************************************************************************************
* SafeAssign
*
* @brief
* NULL pointer safe assignment for 64bit values
***************************************************************************************************
*/
static inline VOID SafeAssign(
UINT_64* pLVal, ///< [in] Pointer to left val
UINT_64 rVal) ///< [in] Right value
{
if (pLVal)
{
*pLVal = rVal;
}
}
/**
***************************************************************************************************
* SafeAssign
*
* @brief
* NULL pointer safe assignment for AddrTileMode
***************************************************************************************************
*/
static inline VOID SafeAssign(
AddrTileMode* pLVal, ///< [in] Pointer to left val
AddrTileMode rVal) ///< [in] Right value
{
if (pLVal)
{
*pLVal = rVal;
}
}
#endif // __ADDR_COMMON_H__

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/*
* Copyright © 2014 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*/
/**
***************************************************************************************************
* @file addrelemlib.h
* @brief Contains the class for element/pixel related functions
***************************************************************************************************
*/
#ifndef __ELEM_LIB_H__
#define __ELEM_LIB_H__
#include "addrinterface.h"
#include "addrobject.h"
#include "addrcommon.h"
class AddrLib;
// The masks for property bits within the Properties INT_32
union ADDR_COMPONENT_FLAGS
{
struct
{
UINT_32 byteAligned : 1; ///< all components are byte aligned
UINT_32 exportNorm : 1; ///< components support R6xx NORM compression
UINT_32 floatComp : 1; ///< there is at least one floating point component
};
UINT_32 value;
};
// Copy from legacy lib's AddrNumberType
enum AddrNumberType
{
// The following number types have the range [-1..1]
ADDR_NO_NUMBER, // This component doesn't exist and has no default value
ADDR_EPSILON, // Force component value to integer 0x00000001
ADDR_ZERO, // Force component value to integer 0x00000000
ADDR_ONE, // Force component value to floating point 1.0
// Above values don't have any bits per component (keep ADDR_ONE the last of these)
ADDR_UNORM, // Unsigned normalized (repeating fraction) full precision
ADDR_SNORM, // Signed normalized (repeating fraction) full precision
ADDR_GAMMA, // Gamma-corrected, full precision
ADDR_UNORM_R5XXRB, // Unsigned normalized (repeating fraction) for r5xx RB
ADDR_SNORM_R5XXRB, // Signed normalized (repeating fraction) for r5xx RB
ADDR_GAMMA_R5XXRB, // Gamma-corrected for r5xx RB (note: unnormalized value)
ADDR_UNORM_R5XXBC, // Unsigned normalized (repeating fraction) for r5xx BC
ADDR_SNORM_R5XXBC, // Signed normalized (repeating fraction) for r5xx BC
ADDR_GAMMA_R5XXBC, // Gamma-corrected for r5xx BC (note: unnormalized value)
ADDR_UNORM_R6XX, // Unsigned normalized (repeating fraction) for R6xx
ADDR_UNORM_R6XXDB, // Unorms for 24-bit depth: one value differs from ADDR_UNORM_R6XX
ADDR_SNORM_R6XX, // Signed normalized (repeating fraction) for R6xx
ADDR_GAMMA8_R6XX, // Gamma-corrected for r6xx
ADDR_GAMMA8_R7XX_TP, // Gamma-corrected for r7xx TP 12bit unorm 8.4.
ADDR_U4FLOATC, // Unsigned float: 4-bit exponent, bias=15, no NaN, clamp [0..1]
ADDR_GAMMA_4SEG, // Gamma-corrected, four segment approximation
ADDR_U0FIXED, // Unsigned 0.N-bit fixed point
// The following number types have large ranges (LEAVE ADDR_USCALED first or fix Finish routine)
ADDR_USCALED, // Unsigned integer converted to/from floating point
ADDR_SSCALED, // Signed integer converted to/from floating point
ADDR_USCALED_R5XXRB, // Unsigned integer to/from floating point for r5xx RB
ADDR_SSCALED_R5XXRB, // Signed integer to/from floating point for r5xx RB
ADDR_UINT_BITS, // Keep in unsigned integer form, clamped to specified range
ADDR_SINT_BITS, // Keep in signed integer form, clamped to specified range
ADDR_UINTBITS, // @@ remove Keep in unsigned integer form, use modulus to reduce bits
ADDR_SINTBITS, // @@ remove Keep in signed integer form, use modulus to reduce bits
// The following number types and ADDR_U4FLOATC have exponents
// (LEAVE ADDR_S8FLOAT first or fix Finish routine)
ADDR_S8FLOAT, // Signed floating point with 8-bit exponent, bias=127
ADDR_S8FLOAT32, // 32-bit IEEE float, passes through NaN values
ADDR_S5FLOAT, // Signed floating point with 5-bit exponent, bias=15
ADDR_S5FLOATM, // Signed floating point with 5-bit exponent, bias=15, no NaN/Inf
ADDR_U5FLOAT, // Signed floating point with 5-bit exponent, bias=15
ADDR_U3FLOATM, // Unsigned floating point with 3-bit exponent, bias=3
ADDR_S5FIXED, // Signed 5.N-bit fixed point, with rounding
ADDR_END_NUMBER // Used for range comparisons
};
// Copy from legacy lib's AddrElement
enum AddrElemMode
{
// These formats allow both packing an unpacking
ADDR_ROUND_BY_HALF, // add 1/2 and truncate when packing this element
ADDR_ROUND_TRUNCATE, // truncate toward 0 for sign/mag, else toward neg
ADDR_ROUND_DITHER, // Pack by dithering -- requires (x,y) position
// These formats only allow unpacking, no packing
ADDR_UNCOMPRESSED, // Elements are not compressed: one data element per pixel/texel
ADDR_EXPANDED, // Elements are split up and stored in multiple data elements
ADDR_PACKED_STD, // Elements are compressed into ExpandX by ExpandY data elements
ADDR_PACKED_REV, // Like ADDR_PACKED, but X order of pixels is reverved
ADDR_PACKED_GBGR, // Elements are compressed 4:2:2 in G1B_G0R order (high to low)
ADDR_PACKED_BGRG, // Elements are compressed 4:2:2 in BG1_RG0 order (high to low)
ADDR_PACKED_BC1, // Each data element is uncompressed to a 4x4 pixel/texel array
ADDR_PACKED_BC2, // Each data element is uncompressed to a 4x4 pixel/texel array
ADDR_PACKED_BC3, // Each data element is uncompressed to a 4x4 pixel/texel array
ADDR_PACKED_BC4, // Each data element is uncompressed to a 4x4 pixel/texel array
ADDR_PACKED_BC5, // Each data element is uncompressed to a 4x4 pixel/texel array
// These formats provide various kinds of compression
ADDR_ZPLANE_R5XX, // Compressed Zplane using r5xx architecture format
ADDR_ZPLANE_R6XX, // Compressed Zplane using r6xx architecture format
//@@ Fill in the compression modes
ADDR_END_ELEMENT // Used for range comparisons
};
enum AddrDepthPlanarType
{
ADDR_DEPTH_PLANAR_NONE = 0, // No plane z/stencl
ADDR_DEPTH_PLANAR_R600 = 1, // R600 z and stencil planes are store within a tile
ADDR_DEPTH_PLANAR_R800 = 2, // R800 has separate z and stencil planes
};
/**
***************************************************************************************************
* ADDR_PIXEL_FORMATINFO
*
* @brief
* Per component info
*
***************************************************************************************************
*/
struct ADDR_PIXEL_FORMATINFO
{
UINT_32 compBit[4];
AddrNumberType numType[4];
UINT_32 compStart[4];
AddrElemMode elemMode;
UINT_32 comps; ///< Number of components
};
/**
***************************************************************************************************
* @brief This class contains asic indepentent element related attributes and operations
***************************************************************************************************
*/
class AddrElemLib : public AddrObject
{
protected:
AddrElemLib(AddrLib* const pAddrLib);
public:
/// Makes this class virtual
virtual ~AddrElemLib();
static AddrElemLib *Create(
const AddrLib* const pAddrLib);
/// The implementation is only for R6xx/R7xx, so make it virtual in case we need for R8xx
BOOL_32 PixGetExportNorm(
AddrColorFormat colorFmt,
AddrSurfaceNumber numberFmt, AddrSurfaceSwap swap) const;
/// Below method are asic independent, so make them just static.
/// Remove static if we need different operation in hwl.
VOID Flt32ToDepthPixel(
AddrDepthFormat format, const ADDR_FLT_32 comps[2], UINT_8 *pPixel) const;
VOID Flt32ToColorPixel(
AddrColorFormat format, AddrSurfaceNumber surfNum, AddrSurfaceSwap surfSwap,
const ADDR_FLT_32 comps[4], UINT_8 *pPixel) const;
static VOID Flt32sToInt32s(
ADDR_FLT_32 value, UINT_32 bits, AddrNumberType numberType, UINT_32* pResult);
static VOID Int32sToPixel(
UINT_32 numComps, UINT_32* pComps, UINT_32* pCompBits, UINT_32* pCompStart,
ADDR_COMPONENT_FLAGS properties, UINT_32 resultBits, UINT_8* pPixel);
VOID PixGetColorCompInfo(
AddrColorFormat format, AddrSurfaceNumber number, AddrSurfaceSwap swap,
ADDR_PIXEL_FORMATINFO* pInfo) const;
VOID PixGetDepthCompInfo(
AddrDepthFormat format, ADDR_PIXEL_FORMATINFO* pInfo) const;
UINT_32 GetBitsPerPixel(
AddrFormat format, AddrElemMode* pElemMode,
UINT_32* pExpandX = NULL, UINT_32* pExpandY = NULL, UINT_32* pBitsUnused = NULL);
static VOID SetClearComps(
ADDR_FLT_32 comps[4], BOOL_32 clearColor, BOOL_32 float32);
VOID AdjustSurfaceInfo(
AddrElemMode elemMode, UINT_32 expandX, UINT_32 expandY,
UINT_32* pBpp, UINT_32* pBasePitch, UINT_32* pWidth, UINT_32* pHeight);
VOID RestoreSurfaceInfo(
AddrElemMode elemMode, UINT_32 expandX, UINT_32 expandY,
UINT_32* pBpp, UINT_32* pWidth, UINT_32* pHeight);
/// Checks if depth and stencil are planar inside a tile
BOOL_32 IsDepthStencilTilePlanar()
{
return (m_depthPlanarType == ADDR_DEPTH_PLANAR_R600) ? TRUE : FALSE;
}
/// Sets m_configFlags, copied from AddrLib
VOID SetConfigFlags(ADDR_CONFIG_FLAGS flags)
{
m_configFlags = flags;
}
static BOOL_32 IsCompressed(AddrFormat format);
static BOOL_32 IsBlockCompressed(AddrFormat format);
static BOOL_32 IsExpand3x(AddrFormat format);
protected:
static VOID GetCompBits(
UINT_32 c0, UINT_32 c1, UINT_32 c2, UINT_32 c3,
ADDR_PIXEL_FORMATINFO* pInfo,
AddrElemMode elemMode = ADDR_ROUND_BY_HALF);
static VOID GetCompType(
AddrColorFormat format, AddrSurfaceNumber numType,
ADDR_PIXEL_FORMATINFO* pInfo);
static VOID GetCompSwap(
AddrSurfaceSwap swap, ADDR_PIXEL_FORMATINFO* pInfo);
static VOID SwapComps(
UINT_32 c0, UINT_32 c1, ADDR_PIXEL_FORMATINFO* pInfo);
private:
UINT_32 m_fp16ExportNorm; ///< If allow FP16 to be reported as EXPORT_NORM
AddrDepthPlanarType m_depthPlanarType;
ADDR_CONFIG_FLAGS m_configFlags; ///< Copy of AddrLib's configFlags
AddrLib* const m_pAddrLib; ///< Pointer to parent addrlib instance
};
#endif

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/*
* Copyright © 2014 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*/
/**
***************************************************************************************************
* @file addrlib.h
* @brief Contains the AddrLib base class definition.
***************************************************************************************************
*/
#ifndef __ADDR_LIB_H__
#define __ADDR_LIB_H__
#include "addrinterface.h"
#include "addrobject.h"
#include "addrelemlib.h"
#if BRAHMA_BUILD
#include "amdgpu_id.h"
#else
#include "atiid.h"
#endif
#ifndef CIASICIDGFXENGINE_R600
#define CIASICIDGFXENGINE_R600 0x00000006
#endif
#ifndef CIASICIDGFXENGINE_R800
#define CIASICIDGFXENGINE_R800 0x00000008
#endif
#ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
#define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
#endif
#ifndef CIASICIDGFXENGINE_SEAISLAND
#define CIASICIDGFXENGINE_SEAISLAND 0x0000000B
#endif
/**
***************************************************************************************************
* @brief Neutral enums that define pipeinterleave
***************************************************************************************************
*/
enum AddrPipeInterleave
{
ADDR_PIPEINTERLEAVE_256B = 256,
ADDR_PIPEINTERLEAVE_512B = 512,
};
/**
***************************************************************************************************
* @brief Neutral enums that define DRAM row size
***************************************************************************************************
*/
enum AddrRowSize
{
ADDR_ROWSIZE_1KB = 1024,
ADDR_ROWSIZE_2KB = 2048,
ADDR_ROWSIZE_4KB = 4096,
ADDR_ROWSIZE_8KB = 8192,
};
/**
***************************************************************************************************
* @brief Neutral enums that define bank interleave
***************************************************************************************************
*/
enum AddrBankInterleave
{
ADDR_BANKINTERLEAVE_1 = 1,
ADDR_BANKINTERLEAVE_2 = 2,
ADDR_BANKINTERLEAVE_4 = 4,
ADDR_BANKINTERLEAVE_8 = 8,
};
/**
***************************************************************************************************
* @brief Neutral enums that define MGPU chip tile size
***************************************************************************************************
*/
enum AddrChipTileSize
{
ADDR_CHIPTILESIZE_16 = 16,
ADDR_CHIPTILESIZE_32 = 32,
ADDR_CHIPTILESIZE_64 = 64,
ADDR_CHIPTILESIZE_128 = 128,
};
/**
***************************************************************************************************
* @brief Neutral enums that define shader engine tile size
***************************************************************************************************
*/
enum AddrEngTileSize
{
ADDR_SE_TILESIZE_16 = 16,
ADDR_SE_TILESIZE_32 = 32,
};
/**
***************************************************************************************************
* @brief Neutral enums that define bank swap size
***************************************************************************************************
*/
enum AddrBankSwapSize
{
ADDR_BANKSWAP_128B = 128,
ADDR_BANKSWAP_256B = 256,
ADDR_BANKSWAP_512B = 512,
ADDR_BANKSWAP_1KB = 1024,
};
/**
***************************************************************************************************
* @brief Neutral enums that define bank swap size
***************************************************************************************************
*/
enum AddrSampleSplitSize
{
ADDR_SAMPLESPLIT_1KB = 1024,
ADDR_SAMPLESPLIT_2KB = 2048,
ADDR_SAMPLESPLIT_4KB = 4096,
ADDR_SAMPLESPLIT_8KB = 8192,
};
/**
***************************************************************************************************
* @brief Flags for AddrTileMode
***************************************************************************************************
*/
struct AddrTileModeFlags
{
UINT_32 thickness : 4;
UINT_32 isLinear : 1;
UINT_32 isMicro : 1;
UINT_32 isMacro : 1;
UINT_32 isMacro3d : 1;
UINT_32 isPrt : 1;
UINT_32 isPrtNoRotation : 1;
UINT_32 isBankSwapped : 1;
};
/**
***************************************************************************************************
* @brief This class contains asic independent address lib functionalities
***************************************************************************************************
*/
class AddrLib : public AddrObject
{
public:
virtual ~AddrLib();
static ADDR_E_RETURNCODE Create(
const ADDR_CREATE_INPUT* pCreateInfo, ADDR_CREATE_OUTPUT* pCreateOut);
/// Pair of Create
VOID Destroy()
{
delete this;
}
static AddrLib* GetAddrLib(
ADDR_HANDLE hLib);
/// Returns AddrLib version (from compiled binary instead include file)
UINT_32 GetVersion()
{
return m_version;
}
/// Returns asic chip family name defined by AddrLib
AddrChipFamily GetAddrChipFamily()
{
return m_chipFamily;
}
/// Returns tileIndex support
BOOL_32 UseTileIndex(INT_32 index) const
{
return m_configFlags.useTileIndex && (index != TileIndexInvalid);
}
/// Returns combined swizzle support
BOOL_32 UseCombinedSwizzle() const
{
return m_configFlags.useCombinedSwizzle;
}
//
// Interface stubs
//
ADDR_E_RETURNCODE ComputeSurfaceInfo(
const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
ADDR_E_RETURNCODE ComputeSurfaceAddrFromCoord(
const ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const;
ADDR_E_RETURNCODE ComputeSurfaceCoordFromAddr(
const ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn,
ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut) const;
ADDR_E_RETURNCODE ComputeSliceTileSwizzle(
const ADDR_COMPUTE_SLICESWIZZLE_INPUT* pIn,
ADDR_COMPUTE_SLICESWIZZLE_OUTPUT* pOut) const;
ADDR_E_RETURNCODE ExtractBankPipeSwizzle(
const ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT* pIn,
ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT* pOut) const;
ADDR_E_RETURNCODE CombineBankPipeSwizzle(
const ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT* pIn,
ADDR_COMBINE_BANKPIPE_SWIZZLE_OUTPUT* pOut) const;
ADDR_E_RETURNCODE ComputeBaseSwizzle(
const ADDR_COMPUTE_BASE_SWIZZLE_INPUT* pIn,
ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT* pOut) const;
ADDR_E_RETURNCODE ComputeFmaskInfo(
const ADDR_COMPUTE_FMASK_INFO_INPUT* pIn,
ADDR_COMPUTE_FMASK_INFO_OUTPUT* pOut);
ADDR_E_RETURNCODE ComputeFmaskAddrFromCoord(
const ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT* pIn,
ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT* pOut) const;
ADDR_E_RETURNCODE ComputeFmaskCoordFromAddr(
const ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT* pIn,
ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT* pOut) const;
ADDR_E_RETURNCODE ConvertTileInfoToHW(
const ADDR_CONVERT_TILEINFOTOHW_INPUT* pIn,
ADDR_CONVERT_TILEINFOTOHW_OUTPUT* pOut) const;
ADDR_E_RETURNCODE ConvertTileIndex(
const ADDR_CONVERT_TILEINDEX_INPUT* pIn,
ADDR_CONVERT_TILEINDEX_OUTPUT* pOut) const;
ADDR_E_RETURNCODE ConvertTileIndex1(
const ADDR_CONVERT_TILEINDEX1_INPUT* pIn,
ADDR_CONVERT_TILEINDEX_OUTPUT* pOut) const;
ADDR_E_RETURNCODE GetTileIndex(
const ADDR_GET_TILEINDEX_INPUT* pIn,
ADDR_GET_TILEINDEX_OUTPUT* pOut) const;
ADDR_E_RETURNCODE ComputeHtileInfo(
const ADDR_COMPUTE_HTILE_INFO_INPUT* pIn,
ADDR_COMPUTE_HTILE_INFO_OUTPUT* pOut) const;
ADDR_E_RETURNCODE ComputeCmaskInfo(
const ADDR_COMPUTE_CMASK_INFO_INPUT* pIn,
ADDR_COMPUTE_CMASK_INFO_OUTPUT* pOut) const;
ADDR_E_RETURNCODE ComputeDccInfo(
const ADDR_COMPUTE_DCCINFO_INPUT* pIn,
ADDR_COMPUTE_DCCINFO_OUTPUT* pOut) const;
ADDR_E_RETURNCODE ComputeHtileAddrFromCoord(
const ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn,
ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut) const;
ADDR_E_RETURNCODE ComputeCmaskAddrFromCoord(
const ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn,
ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut) const;
ADDR_E_RETURNCODE ComputeHtileCoordFromAddr(
const ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn,
ADDR_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut) const;
ADDR_E_RETURNCODE ComputeCmaskCoordFromAddr(
const ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT* pIn,
ADDR_COMPUTE_CMASK_COORDFROMADDR_OUTPUT* pOut) const;
ADDR_E_RETURNCODE ComputePrtInfo(
const ADDR_PRT_INFO_INPUT* pIn,
ADDR_PRT_INFO_OUTPUT* pOut) const;
ADDR_E_RETURNCODE Flt32ToDepthPixel(
const ELEM_FLT32TODEPTHPIXEL_INPUT* pIn,
ELEM_FLT32TODEPTHPIXEL_OUTPUT* pOut) const;
ADDR_E_RETURNCODE Flt32ToColorPixel(
const ELEM_FLT32TOCOLORPIXEL_INPUT* pIn,
ELEM_FLT32TOCOLORPIXEL_OUTPUT* pOut) const;
BOOL_32 GetExportNorm(
const ELEM_GETEXPORTNORM_INPUT* pIn) const;
protected:
AddrLib(); // Constructor is protected
AddrLib(const AddrClient* pClient);
/// Pure Virtual function for Hwl computing surface info
virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfo(
const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const = 0;
/// Pure Virtual function for Hwl computing surface address from coord
virtual ADDR_E_RETURNCODE HwlComputeSurfaceAddrFromCoord(
const ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const = 0;
/// Pure Virtual function for Hwl computing surface coord from address
virtual ADDR_E_RETURNCODE HwlComputeSurfaceCoordFromAddr(
const ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn,
ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut) const = 0;
/// Pure Virtual function for Hwl computing surface tile swizzle
virtual ADDR_E_RETURNCODE HwlComputeSliceTileSwizzle(
const ADDR_COMPUTE_SLICESWIZZLE_INPUT* pIn,
ADDR_COMPUTE_SLICESWIZZLE_OUTPUT* pOut) const = 0;
/// Pure Virtual function for Hwl extracting bank/pipe swizzle from base256b
virtual ADDR_E_RETURNCODE HwlExtractBankPipeSwizzle(
const ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT* pIn,
ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT* pOut) const = 0;
/// Pure Virtual function for Hwl combining bank/pipe swizzle
virtual ADDR_E_RETURNCODE HwlCombineBankPipeSwizzle(
UINT_32 bankSwizzle, UINT_32 pipeSwizzle, ADDR_TILEINFO* pTileInfo,
UINT_64 baseAddr, UINT_32* pTileSwizzle) const = 0;
/// Pure Virtual function for Hwl computing base swizzle
virtual ADDR_E_RETURNCODE HwlComputeBaseSwizzle(
const ADDR_COMPUTE_BASE_SWIZZLE_INPUT* pIn,
ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT* pOut) const = 0;
/// Pure Virtual function for Hwl computing HTILE base align
virtual UINT_32 HwlComputeHtileBaseAlign(
BOOL_32 isTcCompatible, BOOL_32 isLinear, ADDR_TILEINFO* pTileInfo) const = 0;
/// Pure Virtual function for Hwl computing HTILE bpp
virtual UINT_32 HwlComputeHtileBpp(
BOOL_32 isWidth8, BOOL_32 isHeight8) const = 0;
/// Pure Virtual function for Hwl computing HTILE bytes
virtual UINT_64 HwlComputeHtileBytes(
UINT_32 pitch, UINT_32 height, UINT_32 bpp,
BOOL_32 isLinear, UINT_32 numSlices, UINT_64* pSliceBytes, UINT_32 baseAlign) const = 0;
/// Pure Virtual function for Hwl computing FMASK info
virtual ADDR_E_RETURNCODE HwlComputeFmaskInfo(
const ADDR_COMPUTE_FMASK_INFO_INPUT* pIn,
ADDR_COMPUTE_FMASK_INFO_OUTPUT* pOut) = 0;
/// Pure Virtual function for Hwl FMASK address from coord
virtual ADDR_E_RETURNCODE HwlComputeFmaskAddrFromCoord(
const ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT* pIn,
ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT* pOut) const = 0;
/// Pure Virtual function for Hwl FMASK coord from address
virtual ADDR_E_RETURNCODE HwlComputeFmaskCoordFromAddr(
const ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT* pIn,
ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT* pOut) const = 0;
/// Pure Virtual function for Hwl convert tile info from real value to HW value
virtual ADDR_E_RETURNCODE HwlConvertTileInfoToHW(
const ADDR_CONVERT_TILEINFOTOHW_INPUT* pIn,
ADDR_CONVERT_TILEINFOTOHW_OUTPUT* pOut) const = 0;
/// Pure Virtual function for Hwl compute mipmap info
virtual BOOL_32 HwlComputeMipLevel(
ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn) const = 0;
/// Pure Virtual function for Hwl compute max cmask blockMax value
virtual BOOL_32 HwlGetMaxCmaskBlockMax() const = 0;
/// Pure Virtual function for Hwl compute fmask bits
virtual UINT_32 HwlComputeFmaskBits(
const ADDR_COMPUTE_FMASK_INFO_INPUT* pIn,
UINT_32* pNumSamples) const = 0;
/// Virtual function to get index (not pure then no need to implement this in all hwls
virtual ADDR_E_RETURNCODE HwlGetTileIndex(
const ADDR_GET_TILEINDEX_INPUT* pIn,
ADDR_GET_TILEINDEX_OUTPUT* pOut) const
{
return ADDR_NOTSUPPORTED;
}
/// Virtual function for Hwl to compute Dcc info
virtual ADDR_E_RETURNCODE HwlComputeDccInfo(
const ADDR_COMPUTE_DCCINFO_INPUT* pIn,
ADDR_COMPUTE_DCCINFO_OUTPUT* pOut) const
{
return ADDR_NOTSUPPORTED;
}
/// Virtual function to get cmask address for tc compatible cmask
virtual ADDR_E_RETURNCODE HwlComputeCmaskAddrFromCoord(
const ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn,
ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut) const
{
return ADDR_NOTSUPPORTED;
}
// Compute attributes
// HTILE
UINT_32 ComputeHtileInfo(
ADDR_HTILE_FLAGS flags,
UINT_32 pitchIn, UINT_32 heightIn, UINT_32 numSlices,
BOOL_32 isLinear, BOOL_32 isWidth8, BOOL_32 isHeight8,
ADDR_TILEINFO* pTileInfo,
UINT_32* pPitchOut, UINT_32* pHeightOut, UINT_64* pHtileBytes,
UINT_32* pMacroWidth = NULL, UINT_32* pMacroHeight = NULL,
UINT_64* pSliceSize = NULL, UINT_32* pBaseAlign = NULL) const;
// CMASK
ADDR_E_RETURNCODE ComputeCmaskInfo(
ADDR_CMASK_FLAGS flags,
UINT_32 pitchIn, UINT_32 heightIn, UINT_32 numSlices, BOOL_32 isLinear,
ADDR_TILEINFO* pTileInfo, UINT_32* pPitchOut, UINT_32* pHeightOut, UINT_64* pCmaskBytes,
UINT_32* pMacroWidth, UINT_32* pMacroHeight, UINT_64* pSliceSize = NULL,
UINT_32* pBaseAlign = NULL, UINT_32* pBlockMax = NULL) const;
virtual VOID HwlComputeTileDataWidthAndHeightLinear(
UINT_32* pMacroWidth, UINT_32* pMacroHeight,
UINT_32 bpp, ADDR_TILEINFO* pTileInfo) const;
// CMASK & HTILE addressing
virtual UINT_64 HwlComputeXmaskAddrFromCoord(
UINT_32 pitch, UINT_32 height, UINT_32 x, UINT_32 y, UINT_32 slice,
UINT_32 numSlices, UINT_32 factor, BOOL_32 isLinear, BOOL_32 isWidth8,
BOOL_32 isHeight8, ADDR_TILEINFO* pTileInfo,
UINT_32* bitPosition) const;
virtual VOID HwlComputeXmaskCoordFromAddr(
UINT_64 addr, UINT_32 bitPosition, UINT_32 pitch, UINT_32 height, UINT_32 numSlices,
UINT_32 factor, BOOL_32 isLinear, BOOL_32 isWidth8, BOOL_32 isHeight8,
ADDR_TILEINFO* pTileInfo, UINT_32* pX, UINT_32* pY, UINT_32* pSlice) const;
// Surface mipmap
VOID ComputeMipLevel(
ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn) const;
/// Pure Virtual function for Hwl checking degrade for base level
virtual BOOL_32 HwlDegradeBaseLevel(
const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn) const = 0;
virtual BOOL_32 HwlOverrideTileMode(
const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,
AddrTileMode* pTileMode,
AddrTileType* pTileType) const
{
// not supported in hwl layer, FALSE for not-overrided
return FALSE;
}
AddrTileMode DegradeLargeThickTile(AddrTileMode tileMode, UINT_32 bpp) const;
VOID PadDimensions(
AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags,
UINT_32 numSamples, ADDR_TILEINFO* pTileInfo, UINT_32 padDims, UINT_32 mipLevel,
UINT_32* pPitch, UINT_32 pitchAlign, UINT_32* pHeight, UINT_32 heightAlign,
UINT_32* pSlices, UINT_32 sliceAlign) const;
virtual VOID HwlPadDimensions(
AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags,
UINT_32 numSamples, ADDR_TILEINFO* pTileInfo, UINT_32 padDims, UINT_32 mipLevel,
UINT_32* pPitch, UINT_32 pitchAlign, UINT_32* pHeight, UINT_32 heightAlign,
UINT_32* pSlices, UINT_32 sliceAlign) const
{
}
//
// Addressing shared for linear/1D tiling
//
UINT_64 ComputeSurfaceAddrFromCoordLinear(
UINT_32 x, UINT_32 y, UINT_32 slice, UINT_32 sample,
UINT_32 bpp, UINT_32 pitch, UINT_32 height, UINT_32 numSlices,
UINT_32* pBitPosition) const;
VOID ComputeSurfaceCoordFromAddrLinear(
UINT_64 addr, UINT_32 bitPosition, UINT_32 bpp,
UINT_32 pitch, UINT_32 height, UINT_32 numSlices,
UINT_32* pX, UINT_32* pY, UINT_32* pSlice, UINT_32* pSample) const;
VOID ComputeSurfaceCoordFromAddrMicroTiled(
UINT_64 addr, UINT_32 bitPosition,
UINT_32 bpp, UINT_32 pitch, UINT_32 height, UINT_32 numSamples,
AddrTileMode tileMode, UINT_32 tileBase, UINT_32 compBits,
UINT_32* pX, UINT_32* pY, UINT_32* pSlice, UINT_32* pSample,
AddrTileType microTileType, BOOL_32 isDepthSampleOrder) const;
UINT_32 ComputePixelIndexWithinMicroTile(
UINT_32 x, UINT_32 y, UINT_32 z,
UINT_32 bpp, AddrTileMode tileMode, AddrTileType microTileType) const;
/// Pure Virtual function for Hwl computing coord from offset inside micro tile
virtual VOID HwlComputePixelCoordFromOffset(
UINT_32 offset, UINT_32 bpp, UINT_32 numSamples,
AddrTileMode tileMode, UINT_32 tileBase, UINT_32 compBits,
UINT_32* pX, UINT_32* pY, UINT_32* pSlice, UINT_32* pSample,
AddrTileType microTileType, BOOL_32 isDepthSampleOrder) const = 0;
//
// Addressing shared by all
//
virtual UINT_32 HwlGetPipes(
const ADDR_TILEINFO* pTileInfo) const;
UINT_32 ComputePipeFromAddr(
UINT_64 addr, UINT_32 numPipes) const;
/// Pure Virtual function for Hwl computing pipe from coord
virtual UINT_32 ComputePipeFromCoord(
UINT_32 x, UINT_32 y, UINT_32 slice, AddrTileMode tileMode,
UINT_32 pipeSwizzle, BOOL_32 flags, ADDR_TILEINFO* pTileInfo) const = 0;
/// Pure Virtual function for Hwl computing coord Y for 8 pipe cmask/htile
virtual UINT_32 HwlComputeXmaskCoordYFrom8Pipe(
UINT_32 pipe, UINT_32 x) const = 0;
//
// Initialization
//
/// Pure Virtual function for Hwl computing internal global parameters from h/w registers
virtual BOOL_32 HwlInitGlobalParams(
const ADDR_CREATE_INPUT* pCreateIn) = 0;
/// Pure Virtual function for Hwl converting chip family
virtual AddrChipFamily HwlConvertChipFamily(UINT_32 uChipFamily, UINT_32 uChipRevision) = 0;
//
// Misc helper
//
static const AddrTileModeFlags m_modeFlags[ADDR_TM_COUNT];
static UINT_32 ComputeSurfaceThickness(
AddrTileMode tileMode);
// Checking tile mode
static BOOL_32 IsMacroTiled(AddrTileMode tileMode);
static BOOL_32 IsMacro3dTiled(AddrTileMode tileMode);
static BOOL_32 IsLinear(AddrTileMode tileMode);
static BOOL_32 IsMicroTiled(AddrTileMode tileMode);
static BOOL_32 IsPrtTileMode(AddrTileMode tileMode);
static BOOL_32 IsPrtNoRotationTileMode(AddrTileMode tileMode);
static UINT_32 Bits2Number(UINT_32 bitNum,...);
static UINT_32 GetNumFragments(UINT_32 numSamples, UINT_32 numFrags)
{
return numFrags != 0 ? numFrags : Max(1u, numSamples);
}
/// Returns pointer of AddrElemLib
AddrElemLib* GetElemLib() const
{
return m_pElemLib;
}
/// Return TRUE if tile info is needed
BOOL_32 UseTileInfo() const
{
return !m_configFlags.ignoreTileInfo;
}
/// Returns fillSizeFields flag
UINT_32 GetFillSizeFieldsFlags() const
{
return m_configFlags.fillSizeFields;
}
/// Adjusts pitch alignment for flipping surface
VOID AdjustPitchAlignment(
ADDR_SURFACE_FLAGS flags, UINT_32* pPitchAlign) const;
/// Overwrite tile config according to tile index
virtual ADDR_E_RETURNCODE HwlSetupTileCfg(
INT_32 index, INT_32 macroModeIndex,
ADDR_TILEINFO* pInfo, AddrTileMode* mode = NULL, AddrTileType* type = NULL) const;
/// Overwrite macro tile config according to tile index
virtual INT_32 HwlComputeMacroModeIndex(
INT_32 index, ADDR_SURFACE_FLAGS flags, UINT_32 bpp, UINT_32 numSamples,
ADDR_TILEINFO* pTileInfo, AddrTileMode *pTileMode = NULL, AddrTileType *pTileType = NULL
) const
{
return TileIndexNoMacroIndex;
}
/// Pre-handler of 3x pitch (96 bit) adjustment
virtual UINT_32 HwlPreHandleBaseLvl3xPitch(
const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn, UINT_32 expPitch) const;
/// Post-handler of 3x pitch adjustment
virtual UINT_32 HwlPostHandleBaseLvl3xPitch(
const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn, UINT_32 expPitch) const;
/// Check miplevel after surface adjustment
ADDR_E_RETURNCODE PostComputeMipLevel(
ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
/// Quad buffer stereo support, has its implementation in ind. layer
virtual BOOL_32 ComputeQbStereoInfo(
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
/// Pure virutual function to compute stereo bank swizzle for right eye
virtual UINT_32 HwlComputeQbStereoRightSwizzle(
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const = 0;
private:
// Disallow the copy constructor
AddrLib(const AddrLib& a);
// Disallow the assignment operator
AddrLib& operator=(const AddrLib& a);
VOID SetAddrChipFamily(UINT_32 uChipFamily, UINT_32 uChipRevision);
UINT_32 ComputeCmaskBaseAlign(
ADDR_CMASK_FLAGS flags, ADDR_TILEINFO* pTileInfo) const;
UINT_64 ComputeCmaskBytes(
UINT_32 pitch, UINT_32 height, UINT_32 numSlices) const;
//
// CMASK/HTILE shared methods
//
VOID ComputeTileDataWidthAndHeight(
UINT_32 bpp, UINT_32 cacheBits, ADDR_TILEINFO* pTileInfo,
UINT_32* pMacroWidth, UINT_32* pMacroHeight) const;
UINT_32 ComputeXmaskCoordYFromPipe(
UINT_32 pipe, UINT_32 x) const;
VOID SetMinPitchAlignPixels(UINT_32 minPitchAlignPixels);
BOOL_32 DegradeBaseLevel(
const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn, AddrTileMode* pTileMode) const;
protected:
AddrLibClass m_class; ///< Store class type (HWL type)
AddrChipFamily m_chipFamily; ///< Chip family translated from the one in atiid.h
UINT_32 m_chipRevision; ///< Revision id from xxx_id.h
UINT_32 m_version; ///< Current version
//
// Global parameters
//
ADDR_CONFIG_FLAGS m_configFlags; ///< Global configuration flags. Note this is setup by
/// AddrLib instead of Client except forceLinearAligned
UINT_32 m_pipes; ///< Number of pipes
UINT_32 m_banks; ///< Number of banks
/// For r800 this is MC_ARB_RAMCFG.NOOFBANK
/// Keep it here to do default parameter calculation
UINT_32 m_pipeInterleaveBytes;
///< Specifies the size of contiguous address space
/// within each tiling pipe when making linear
/// accesses. (Formerly Group Size)
UINT_32 m_rowSize; ///< DRAM row size, in bytes
UINT_32 m_minPitchAlignPixels; ///< Minimum pitch alignment in pixels
UINT_32 m_maxSamples; ///< Max numSamples
private:
AddrElemLib* m_pElemLib; ///< Element Lib pointer
};
AddrLib* AddrSIHwlInit (const AddrClient* pClient);
AddrLib* AddrCIHwlInit (const AddrClient* pClient);
#endif

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@ -0,0 +1,246 @@
/*
* Copyright © 2014 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*/
/**
***************************************************************************************************
* @file addrobject.cpp
* @brief Contains the AddrObject base class implementation.
***************************************************************************************************
*/
#include "addrinterface.h"
#include "addrobject.h"
/**
***************************************************************************************************
* AddrObject::AddrObject
*
* @brief
* Constructor for the AddrObject class.
***************************************************************************************************
*/
AddrObject::AddrObject()
{
m_client.handle = NULL;
m_client.callbacks.allocSysMem = NULL;
m_client.callbacks.freeSysMem = NULL;
m_client.callbacks.debugPrint = NULL;
}
/**
***************************************************************************************************
* AddrObject::AddrObject
*
* @brief
* Constructor for the AddrObject class.
***************************************************************************************************
*/
AddrObject::AddrObject(const AddrClient* pClient)
{
m_client = *pClient;
}
/**
***************************************************************************************************
* AddrObject::~AddrObject
*
* @brief
* Destructor for the AddrObject class.
***************************************************************************************************
*/
AddrObject::~AddrObject()
{
}
/**
***************************************************************************************************
* AddrObject::ClientAlloc
*
* @brief
* Calls instanced allocSysMem inside AddrClient
***************************************************************************************************
*/
VOID* AddrObject::ClientAlloc(
size_t objSize, ///< [in] Size to allocate
const AddrClient* pClient) ///< [in] Client pointer
{
VOID* pObjMem = NULL;
if (pClient->callbacks.allocSysMem != NULL)
{
ADDR_ALLOCSYSMEM_INPUT allocInput = {0};
allocInput.size = sizeof(ADDR_ALLOCSYSMEM_INPUT);
allocInput.flags.value = 0;
allocInput.sizeInBytes = static_cast<UINT_32>(objSize);
allocInput.hClient = pClient->handle;
pObjMem = pClient->callbacks.allocSysMem(&allocInput);
}
return pObjMem;
}
/**
***************************************************************************************************
* AddrObject::AddrMalloc
*
* @brief
* A wrapper of ClientAlloc
***************************************************************************************************
*/
VOID* AddrObject::AddrMalloc(
size_t objSize) const ///< [in] Size to allocate
{
return ClientAlloc(objSize, &m_client);;
}
/**
***************************************************************************************************
* AddrObject::ClientFree
*
* @brief
* Calls freeSysMem inside AddrClient
***************************************************************************************************
*/
VOID AddrObject::ClientFree(
VOID* pObjMem, ///< [in] User virtual address to free.
const AddrClient* pClient) ///< [in] Client pointer
{
if (pClient->callbacks.freeSysMem != NULL)
{
if (pObjMem != NULL)
{
ADDR_FREESYSMEM_INPUT freeInput = {0};
freeInput.size = sizeof(ADDR_FREESYSMEM_INPUT);
freeInput.hClient = pClient->handle;
freeInput.pVirtAddr = pObjMem;
pClient->callbacks.freeSysMem(&freeInput);
}
}
}
/**
***************************************************************************************************
* AddrObject::AddrFree
*
* @brief
* A wrapper of ClientFree
***************************************************************************************************
*/
VOID AddrObject::AddrFree(
VOID* pObjMem) const ///< [in] User virtual address to free.
{
ClientFree(pObjMem, &m_client);
}
/**
***************************************************************************************************
* AddrObject::operator new
*
* @brief
* Allocates memory needed for AddrObject object. (with ADDR_CLIENT_HANDLE)
*
* @return
* Returns NULL if unsuccessful.
***************************************************************************************************
*/
VOID* AddrObject::operator new(
size_t objSize, ///< [in] Size to allocate
const AddrClient* pClient) ///< [in] Client pointer
{
return ClientAlloc(objSize, pClient);
}
/**
***************************************************************************************************
* AddrObject::operator delete
*
* @brief
* Frees AddrObject object memory.
***************************************************************************************************
*/
VOID AddrObject::operator delete(
VOID* pObjMem, ///< [in] User virtual address to free.
const AddrClient* pClient) ///< [in] Client handle
{
ClientFree(pObjMem, pClient);
}
/**
***************************************************************************************************
* AddrObject::operator delete
*
* @brief
* Frees AddrObject object memory.
***************************************************************************************************
*/
VOID AddrObject::operator delete(
VOID* pObjMem) ///< [in] User virtual address to free.
{
AddrObject* pObj = static_cast<AddrObject*>(pObjMem);
ClientFree(pObjMem, &pObj->m_client);
}
/**
***************************************************************************************************
* AddrObject::DebugPrint
*
* @brief
* Print debug message
*
* @return
* N/A
***************************************************************************************************
*/
VOID AddrObject::DebugPrint(
const CHAR* pDebugString, ///< [in] Debug string
...) const
{
#if DEBUG
if (m_client.callbacks.debugPrint != NULL)
{
va_list ap;
va_start(ap, pDebugString);
ADDR_DEBUGPRINT_INPUT debugPrintInput = {0};
debugPrintInput.size = sizeof(ADDR_DEBUGPRINT_INPUT);
debugPrintInput.pDebugString = const_cast<CHAR*>(pDebugString);
debugPrintInput.hClient = m_client.handle;
va_copy(debugPrintInput.ap, ap);
m_client.callbacks.debugPrint(&debugPrintInput);
va_end(ap);
}
#endif
}

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/*
* Copyright © 2014 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*/
/**
***************************************************************************************************
* @file addrobject.h
* @brief Contains the AddrObject base class definition.
***************************************************************************************************
*/
#ifndef __ADDR_OBJECT_H__
#define __ADDR_OBJECT_H__
#include "addrtypes.h"
#include "addrcommon.h"
/**
***************************************************************************************************
* @brief This structure contains client specific data
***************************************************************************************************
*/
struct AddrClient
{
ADDR_CLIENT_HANDLE handle;
ADDR_CALLBACKS callbacks;
};
/**
***************************************************************************************************
* @brief This class is the base class for all ADDR class objects.
***************************************************************************************************
*/
class AddrObject
{
public:
AddrObject();
AddrObject(const AddrClient* pClient);
virtual ~AddrObject();
VOID* operator new(size_t size, const AddrClient* pClient);
VOID operator delete(VOID* pObj, const AddrClient* pClient);
VOID operator delete(VOID* pObj);
VOID* AddrMalloc(size_t size) const;
VOID AddrFree(VOID* pObj) const;
VOID DebugPrint(
const CHAR* pDebugString,
...) const;
const AddrClient* GetClient() const {return &m_client;}
protected:
AddrClient m_client;
private:
static VOID* ClientAlloc(size_t size, const AddrClient* pClient);
static VOID ClientFree(VOID* pObj, const AddrClient* pClient);
// disallow the copy constructor
AddrObject(const AddrObject& a);
// disallow the assignment operator
AddrObject& operator=(const AddrObject& a);
};
#endif

155
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#if !defined (__SI_GB_REG_H__)
#define __SI_GB_REG_H__
/*
* Copyright © 2014 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*/
//
// Make sure the necessary endian defines are there.
//
#if defined(LITTLEENDIAN_CPU)
#elif defined(BIGENDIAN_CPU)
#else
#error "BIGENDIAN_CPU or LITTLEENDIAN_CPU must be defined"
#endif
/*
* GB_ADDR_CONFIG struct
*/
#if defined(LITTLEENDIAN_CPU)
typedef struct _GB_ADDR_CONFIG_T {
unsigned int num_pipes : 3;
unsigned int : 1;
unsigned int pipe_interleave_size : 3;
unsigned int : 1;
unsigned int bank_interleave_size : 3;
unsigned int : 1;
unsigned int num_shader_engines : 2;
unsigned int : 2;
unsigned int shader_engine_tile_size : 3;
unsigned int : 1;
unsigned int num_gpus : 3;
unsigned int : 1;
unsigned int multi_gpu_tile_size : 2;
unsigned int : 2;
unsigned int row_size : 2;
unsigned int num_lower_pipes : 1;
unsigned int : 1;
} GB_ADDR_CONFIG_T;
#elif defined(BIGENDIAN_CPU)
typedef struct _GB_ADDR_CONFIG_T {
unsigned int : 1;
unsigned int num_lower_pipes : 1;
unsigned int row_size : 2;
unsigned int : 2;
unsigned int multi_gpu_tile_size : 2;
unsigned int : 1;
unsigned int num_gpus : 3;
unsigned int : 1;
unsigned int shader_engine_tile_size : 3;
unsigned int : 2;
unsigned int num_shader_engines : 2;
unsigned int : 1;
unsigned int bank_interleave_size : 3;
unsigned int : 1;
unsigned int pipe_interleave_size : 3;
unsigned int : 1;
unsigned int num_pipes : 3;
} GB_ADDR_CONFIG_T;
#endif
typedef union {
unsigned int val : 32;
GB_ADDR_CONFIG_T f;
} GB_ADDR_CONFIG;
#if defined(LITTLEENDIAN_CPU)
typedef struct _GB_TILE_MODE_T {
unsigned int micro_tile_mode : 2;
unsigned int array_mode : 4;
unsigned int pipe_config : 5;
unsigned int tile_split : 3;
unsigned int bank_width : 2;
unsigned int bank_height : 2;
unsigned int macro_tile_aspect : 2;
unsigned int num_banks : 2;
unsigned int micro_tile_mode_new : 3;
unsigned int sample_split : 2;
unsigned int : 5;
} GB_TILE_MODE_T;
typedef struct _GB_MACROTILE_MODE_T {
unsigned int bank_width : 2;
unsigned int bank_height : 2;
unsigned int macro_tile_aspect : 2;
unsigned int num_banks : 2;
unsigned int : 24;
} GB_MACROTILE_MODE_T;
#elif defined(BIGENDIAN_CPU)
typedef struct _GB_TILE_MODE_T {
unsigned int : 5;
unsigned int sample_split : 2;
unsigned int micro_tile_mode_new : 3;
unsigned int num_banks : 2;
unsigned int macro_tile_aspect : 2;
unsigned int bank_height : 2;
unsigned int bank_width : 2;
unsigned int tile_split : 3;
unsigned int pipe_config : 5;
unsigned int array_mode : 4;
unsigned int micro_tile_mode : 2;
} GB_TILE_MODE_T;
typedef struct _GB_MACROTILE_MODE_T {
unsigned int : 24;
unsigned int num_banks : 2;
unsigned int macro_tile_aspect : 2;
unsigned int bank_height : 2;
unsigned int bank_width : 2;
} GB_MACROTILE_MODE_T;
#endif
typedef union {
unsigned int val : 32;
GB_TILE_MODE_T f;
} GB_TILE_MODE;
typedef union {
unsigned int val : 32;
GB_MACROTILE_MODE_T f;
} GB_MACROTILE_MODE;
#endif

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/*
* Copyright © 2014 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*/
#ifndef _lnx_common_defs_h_
#define _lnx_common_defs_h_
#if DBG
#include <stdarg.h> // We do not have any choice: need variable
// number of parameters support for debug
// build.
#endif // #if DBG
//
// -------------- External functions from Linux kernel driver ----------------
//
// Note: The definitions/declararions below must match the original ones.
#ifdef __cplusplus
extern "C" {
#endif
typedef unsigned long __ke_size_t; // as it is defined in firegl_public.h
typedef int __kernel_ptrdiff_t; // as it is defined in posix_types.h
#if !defined(ATI_API_CALL)
#define ATI_API_CALL __attribute__((regparm(0)))
#endif
extern void * ATI_API_CALL __ke_memset(void* s, int c, __ke_size_t count);
extern void * ATI_API_CALL __ke_memcpy(void* d, const void* s, __ke_size_t count);
extern ATI_API_CALL __ke_size_t __ke_strlen(const char *s);
extern char* ATI_API_CALL __ke_strcpy(char* d, const char* s);
extern char* ATI_API_CALL __ke_strncpy(char* d, const char* s, __ke_size_t count);
extern void __ke_printk(const char* fmt, ...);
extern int ATI_API_CALL __ke_snprintf(char* buf, __ke_size_t size, const char* fmt, ...);
extern int ATI_API_CALL KCL_CopyFromUserSpace(void* to, const void* from, __ke_size_t size);
extern int ATI_API_CALL KCL_CopyToUserSpace(void* to, const void* from, __ke_size_t size);
#define __ke_copy_from_user KCL_CopyFromUserSpace
#define __ke_copy_to_user KCL_CopyToUserSpace
extern int ATI_API_CALL __ke_verify_area(int type, const void * addr, unsigned long size);
extern unsigned long ATI_API_CALL KAS_GetTickCounter(void);
extern unsigned long ATI_API_CALL KAS_GetTicksPerSecond(void);
#if DBG
extern int ATI_API_CALL __ke_vsnprintf(char *buf, __ke_size_t size, const char *fmt, va_list ap);
#define vsnprintf(_dst, _size, _fmt, varg) __ke_snprintf(_dst, _size, _fmt, varg)
#endif // #if DBG
// Note: This function is not defined in firegl_public.h.
void firegl_hardwareHangRecovery(void);
#ifdef __cplusplus
}
#endif
//
// -------------------------- C/C++ standard typedefs ----------------------------
//
#ifdef __SIZE_TYPE__
typedef __SIZE_TYPE__ size_t;
#else // #ifdef __SIZE_TYPE__
typedef unsigned int size_t;
#endif // #ifdef __SIZE_TYPE__
#ifdef __PTRDIFF_TYPE__
typedef __PTRDIFF_TYPE__ ptrdiff_t;
#else // #ifdef __PTRDIFF_TYPE__
typedef int ptrdiff_t;
#endif // #ifdef __PTRDIFF_TYPE__
#ifndef NULL
#ifdef __cplusplus
#define NULL __null
#else
#define NULL ((void *)0)
#endif
#endif
//
// ------------------------- C/C++ standard macros ---------------------------
//
#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER) // as it is defined in stddef.h
#define CHAR_BIT 8 // as it is defined in limits.h
//
// --------------------------------- C RTL -----------------------------------
//
#define memset(_p, _v, _n) __ke_memset(_p, _v, _n)
#define memcpy(_d, _s, _n) __ke_memcpy(_d, _s, _n)
#define strlen(_s) __ke_strlen(_s)
#define strcpy(_d, _s) __ke_strcpy(_d, _s)
#define strncpy(_d, _s, _n) __ke_strncpy(_d, _s, _n)
// Note: C99 supports macros with variable number of arguments. GCC also supports this C99 feature as
// C++ extension.
#define snprintf(_dst, _size, _fmt, arg...) __ke_snprintf(_dst, _size, _fmt, ##arg)
#endif // #ifdef _lnx_common_defs_h_

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/*
* Copyright © 2014 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*/
#if !defined (SI_CI_VI_MERGED_ENUM_HEADER)
#define SI_CI_VI_MERGED_ENUM_HEADER
typedef enum PipeInterleaveSize {
ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x00000000,
ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x00000001,
} PipeInterleaveSize;
typedef enum RowSize {
ADDR_CONFIG_1KB_ROW = 0x00000000,
ADDR_CONFIG_2KB_ROW = 0x00000001,
ADDR_CONFIG_4KB_ROW = 0x00000002,
} RowSize;
#endif

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/*
* Copyright © 2014 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*/
/**
***************************************************************************************************
* @file ciaddrlib.h
* @brief Contains the CIAddrLib class definition.
***************************************************************************************************
*/
#ifndef __CI_ADDR_LIB_H__
#define __CI_ADDR_LIB_H__
#include "addrlib.h"
#include "siaddrlib.h"
/**
***************************************************************************************************
* @brief CI specific settings structure.
***************************************************************************************************
*/
struct CIChipSettings
{
struct
{
UINT_32 isSeaIsland : 1;
UINT_32 isBonaire : 1;
UINT_32 isKaveri : 1;
UINT_32 isSpectre : 1;
UINT_32 isSpooky : 1;
UINT_32 isKalindi : 1;
// Hawaii is GFXIP 7.2, similar with CI (Bonaire)
UINT_32 isHawaii : 1;
// VI
UINT_32 isVolcanicIslands : 1;
UINT_32 isIceland : 1;
UINT_32 isTonga : 1;
// VI fusion (Carrizo)
UINT_32 isCarrizo : 1;
};
};
/**
***************************************************************************************************
* @brief This class is the CI specific address library
* function set.
***************************************************************************************************
*/
class CIAddrLib : public SIAddrLib
{
public:
/// Creates CIAddrLib object
static AddrLib* CreateObj(const AddrClient* pClient)
{
return new(pClient) CIAddrLib(pClient);
}
private:
CIAddrLib(const AddrClient* pClient);
virtual ~CIAddrLib();
protected:
// Hwl interface - defined in AddrLib
virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfo(
const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
virtual ADDR_E_RETURNCODE HwlComputeFmaskInfo(
const ADDR_COMPUTE_FMASK_INFO_INPUT* pIn,
ADDR_COMPUTE_FMASK_INFO_OUTPUT* pOut);
virtual AddrChipFamily HwlConvertChipFamily(
UINT_32 uChipFamily, UINT_32 uChipRevision);
virtual BOOL_32 HwlInitGlobalParams(
const ADDR_CREATE_INPUT* pCreateIn);
virtual ADDR_E_RETURNCODE HwlSetupTileCfg(
INT_32 index, INT_32 macroModeIndex, ADDR_TILEINFO* pInfo,
AddrTileMode* pMode = 0, AddrTileType* pType = 0) const;
virtual VOID HwlComputeTileDataWidthAndHeightLinear(
UINT_32* pMacroWidth, UINT_32* pMacroHeight,
UINT_32 bpp, ADDR_TILEINFO* pTileInfo) const;
virtual INT_32 HwlComputeMacroModeIndex(
INT_32 tileIndex, ADDR_SURFACE_FLAGS flags, UINT_32 bpp, UINT_32 numSamples,
ADDR_TILEINFO* pTileInfo, AddrTileMode* pTileMode = NULL, AddrTileType* pTileType = NULL
) const;
// Sub-hwl interface - defined in EgBasedAddrLib
virtual VOID HwlSetupTileInfo(
AddrTileMode tileMode, ADDR_SURFACE_FLAGS flags,
UINT_32 bpp, UINT_32 pitch, UINT_32 height, UINT_32 numSamples,
ADDR_TILEINFO* inputTileInfo, ADDR_TILEINFO* outputTileInfo,
AddrTileType inTileType, ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
virtual INT_32 HwlPostCheckTileIndex(
const ADDR_TILEINFO* pInfo, AddrTileMode mode, AddrTileType type,
INT curIndex = TileIndexInvalid) const;
virtual VOID HwlFmaskPreThunkSurfInfo(
const ADDR_COMPUTE_FMASK_INFO_INPUT* pFmaskIn,
const ADDR_COMPUTE_FMASK_INFO_OUTPUT* pFmaskOut,
ADDR_COMPUTE_SURFACE_INFO_INPUT* pSurfIn,
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pSurfOut) const;
virtual VOID HwlFmaskPostThunkSurfInfo(
const ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pSurfOut,
ADDR_COMPUTE_FMASK_INFO_OUTPUT* pFmaskOut) const;
virtual AddrTileMode HwlDegradeThickTileMode(
AddrTileMode baseTileMode, UINT_32 numSlices, UINT_32* pBytesPerTile) const;
virtual BOOL_32 HwlOverrideTileMode(
const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,
AddrTileMode* pTileMode,
AddrTileType* pTileType) const;
virtual BOOL_32 HwlStereoCheckRightOffsetPadding() const;
virtual ADDR_E_RETURNCODE HwlComputeDccInfo(
const ADDR_COMPUTE_DCCINFO_INPUT* pIn,
ADDR_COMPUTE_DCCINFO_OUTPUT* pOut) const;
virtual ADDR_E_RETURNCODE HwlComputeCmaskAddrFromCoord(
const ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn,
ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut) const;
protected:
virtual VOID HwlPadDimensions(
AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags,
UINT_32 numSamples, ADDR_TILEINFO* pTileInfo, UINT_32 padDims, UINT_32 mipLevel,
UINT_32* pPitch, UINT_32 pitchAlign, UINT_32* pHeight, UINT_32 heightAlign,
UINT_32* pSlices, UINT_32 sliceAlign) const;
private:
VOID ReadGbTileMode(
UINT_32 regValue, ADDR_TILECONFIG* pCfg) const;
VOID ReadGbMacroTileCfg(
UINT_32 regValue, ADDR_TILEINFO* pCfg) const;
BOOL_32 InitTileSettingTable(
const UINT_32 *pSetting, UINT_32 noOfEntries);
BOOL_32 InitMacroTileCfgTable(
const UINT_32 *pSetting, UINT_32 noOfEntries);
UINT_64 HwlComputeMetadataNibbleAddress(
UINT_64 uncompressedDataByteAddress,
UINT_64 dataBaseByteAddress,
UINT_64 metadataBaseByteAddress,
UINT_32 metadataBitSize,
UINT_32 elementBitSize,
UINT_32 blockByteSize,
UINT_32 pipeInterleaveBytes,
UINT_32 numOfPipes,
UINT_32 numOfBanks,
UINT_32 numOfSamplesPerSplit) const;
static const UINT_32 MacroTileTableSize = 16;
ADDR_TILEINFO m_macroTileTable[MacroTileTableSize];
UINT_32 m_noOfMacroEntries;
BOOL_32 m_allowNonDispThickModes;
CIChipSettings m_settings;
};
#endif

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/*
* Copyright © 2014 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*/
/**
***************************************************************************************************
* @file egbaddrlib.h
* @brief Contains the EgBasedAddrLib class definition.
***************************************************************************************************
*/
#ifndef __EG_BASED_ADDR_LIB_H__
#define __EG_BASED_ADDR_LIB_H__
#include "addrlib.h"
/// Structures for functions
struct CoordFromBankPipe
{
UINT_32 xBits : 3;
UINT_32 yBits : 4;
UINT_32 xBit3 : 1;
UINT_32 xBit4 : 1;
UINT_32 xBit5 : 1;
UINT_32 yBit3 : 1;
UINT_32 yBit4 : 1;
UINT_32 yBit5 : 1;
UINT_32 yBit6 : 1;
};
/**
***************************************************************************************************
* @brief This class is the Evergreen based address library
* @note Abstract class
***************************************************************************************************
*/
class EgBasedAddrLib : public AddrLib
{
protected:
EgBasedAddrLib(const AddrClient* pClient);
virtual ~EgBasedAddrLib();
public:
/// Surface info functions
// NOTE: DispatchComputeSurfaceInfo using TileInfo takes both an input and an output.
// On input:
// One or more fields may be 0 to be calculated/defaulted - pre-SI h/w.
// H/W using tile mode index only accepts none or all 0's - SI and newer h/w.
// It then returns the actual tiling configuration used.
// Other methods' TileInfo must be valid on entry
BOOL_32 DispatchComputeSurfaceInfo(
const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
ADDR_E_RETURNCODE DispatchComputeFmaskInfo(
const ADDR_COMPUTE_FMASK_INFO_INPUT* pIn,
ADDR_COMPUTE_FMASK_INFO_OUTPUT* pOut);
protected:
// Hwl interface
virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfo(
const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
virtual ADDR_E_RETURNCODE HwlComputeSurfaceAddrFromCoord(
const ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const;
virtual ADDR_E_RETURNCODE HwlComputeSurfaceCoordFromAddr(
const ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn,
ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut) const;
virtual ADDR_E_RETURNCODE HwlComputeSliceTileSwizzle(
const ADDR_COMPUTE_SLICESWIZZLE_INPUT* pIn,
ADDR_COMPUTE_SLICESWIZZLE_OUTPUT* pOut) const;
virtual ADDR_E_RETURNCODE HwlExtractBankPipeSwizzle(
const ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT* pIn,
ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT* pOut) const;
virtual ADDR_E_RETURNCODE HwlCombineBankPipeSwizzle(
UINT_32 bankSwizzle, UINT_32 pipeSwizzle, ADDR_TILEINFO* pTileInfo,
UINT_64 baseAddr, UINT_32* pTileSwizzle) const;
virtual ADDR_E_RETURNCODE HwlComputeBaseSwizzle(
const ADDR_COMPUTE_BASE_SWIZZLE_INPUT* pIn,
ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT* pOut) const;
virtual ADDR_E_RETURNCODE HwlConvertTileInfoToHW(
const ADDR_CONVERT_TILEINFOTOHW_INPUT* pIn,
ADDR_CONVERT_TILEINFOTOHW_OUTPUT* pOut) const;
virtual UINT_32 HwlComputeHtileBpp(
BOOL_32 isWidth8, BOOL_32 isHeight8) const;
virtual UINT_32 HwlComputeHtileBaseAlign(
BOOL_32 isTcCompatible, BOOL_32 isLinear, ADDR_TILEINFO* pTileInfo) const;
virtual ADDR_E_RETURNCODE HwlComputeFmaskInfo(
const ADDR_COMPUTE_FMASK_INFO_INPUT* pIn,
ADDR_COMPUTE_FMASK_INFO_OUTPUT* pOut);
virtual ADDR_E_RETURNCODE HwlComputeFmaskAddrFromCoord(
const ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT* pIn,
ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT* pOut) const;
virtual ADDR_E_RETURNCODE HwlComputeFmaskCoordFromAddr(
const ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT* pIn,
ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT* pOut) const;
virtual BOOL_32 HwlDegradeBaseLevel(
const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn) const;
virtual UINT_32 HwlComputeQbStereoRightSwizzle(
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pInfo) const;
virtual VOID HwlComputePixelCoordFromOffset(
UINT_32 offset, UINT_32 bpp, UINT_32 numSamples,
AddrTileMode tileMode, UINT_32 tileBase, UINT_32 compBits,
UINT_32* pX, UINT_32* pY, UINT_32* pSlice, UINT_32* pSample,
AddrTileType microTileType, BOOL_32 isDepthSampleOrder) const;
/// Return Cmask block max
virtual BOOL_32 HwlGetMaxCmaskBlockMax() const
{
return 16383; // 14 bits
}
// Sub-hwl interface
/// Pure virtual function to setup tile info (indices) if client requests to do so
virtual VOID HwlSetupTileInfo(
AddrTileMode tileMode, ADDR_SURFACE_FLAGS flags,
UINT_32 bpp, UINT_32 pitch, UINT_32 height, UINT_32 numSamples,
ADDR_TILEINFO* inputTileInfo, ADDR_TILEINFO* outputTileInfo,
AddrTileType inTileType, ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const = 0;
/// Pure virtual function to get pitch alignment for linear modes
virtual UINT_32 HwlGetPitchAlignmentLinear(UINT_32 bpp, ADDR_SURFACE_FLAGS flags) const = 0;
/// Pure virtual function to get size adjustment for linear modes
virtual UINT_64 HwlGetSizeAdjustmentLinear(
AddrTileMode tileMode,
UINT_32 bpp, UINT_32 numSamples, UINT_32 baseAlign, UINT_32 pitchAlign,
UINT_32 *pPitch, UINT_32 *pHeight, UINT_32 *pHeightAlign) const = 0;
virtual UINT_32 HwlGetPitchAlignmentMicroTiled(
AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags, UINT_32 numSamples) const;
virtual UINT_64 HwlGetSizeAdjustmentMicroTiled(
UINT_32 thickness, UINT_32 bpp, ADDR_SURFACE_FLAGS flags, UINT_32 numSamples,
UINT_32 baseAlign, UINT_32 pitchAlign,
UINT_32 *pPitch, UINT_32 *pHeight) const;
/// Pure virtual function to do extra sanity check
virtual BOOL_32 HwlSanityCheckMacroTiled(
ADDR_TILEINFO* pTileInfo) const = 0;
/// Pure virtual function to check current level to be the last macro tiled one
virtual VOID HwlCheckLastMacroTiledLvl(
const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const = 0;
/// Adjusts bank before bank is modified by rotation
virtual UINT_32 HwlPreAdjustBank(
UINT_32 tileX, UINT_32 bank, ADDR_TILEINFO* pTileInfo) const = 0;
virtual VOID HwlComputeSurfaceCoord2DFromBankPipe(
AddrTileMode tileMode, UINT_32* pX, UINT_32* pY, UINT_32 slice,
UINT_32 bank, UINT_32 pipe,
UINT_32 bankSwizzle, UINT_32 pipeSwizzle, UINT_32 tileSlices,
BOOL_32 ignoreSE,
ADDR_TILEINFO* pTileInfo) const = 0;
virtual BOOL_32 HwlTileInfoEqual(
const ADDR_TILEINFO* pLeft, const ADDR_TILEINFO* pRight) const;
virtual AddrTileMode HwlDegradeThickTileMode(
AddrTileMode baseTileMode, UINT_32 numSlices, UINT_32* pBytesPerTile) const;
virtual INT_32 HwlPostCheckTileIndex(
const ADDR_TILEINFO* pInfo, AddrTileMode mode, AddrTileType type,
INT curIndex = TileIndexInvalid) const
{
return TileIndexInvalid;
}
virtual VOID HwlFmaskPreThunkSurfInfo(
const ADDR_COMPUTE_FMASK_INFO_INPUT* pFmaskIn,
const ADDR_COMPUTE_FMASK_INFO_OUTPUT* pFmaskOut,
ADDR_COMPUTE_SURFACE_INFO_INPUT* pSurfIn,
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pSurfOut) const
{
}
virtual VOID HwlFmaskPostThunkSurfInfo(
const ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pSurfOut,
ADDR_COMPUTE_FMASK_INFO_OUTPUT* pFmaskOut) const
{
}
/// Virtual function to check if the height needs extra padding
/// for stereo right eye offset, to avoid bank pipe swizzle
virtual BOOL_32 HwlStereoCheckRightOffsetPadding() const
{
return FALSE;
}
virtual BOOL_32 HwlReduceBankWidthHeight(
UINT_32 tileSize, UINT_32 bpp, ADDR_SURFACE_FLAGS flags, UINT_32 numSamples,
UINT_32 bankHeightAlign, UINT_32 pipes,
ADDR_TILEINFO* pTileInfo) const;
// Protected non-virtual functions
/// Mip level functions
AddrTileMode ComputeSurfaceMipLevelTileMode(
AddrTileMode baseTileMode, UINT_32 bpp,
UINT_32 pitch, UINT_32 height, UINT_32 numSlices, UINT_32 numSamples,
UINT_32 pitchAlign, UINT_32 heightAlign,
ADDR_TILEINFO* pTileInfo) const;
/// Swizzle functions
VOID ExtractBankPipeSwizzle(
UINT_32 base256b, ADDR_TILEINFO* pTileInfo,
UINT_32* pBankSwizzle, UINT_32* pPipeSwizzle) const;
UINT_32 GetBankPipeSwizzle(
UINT_32 bankSwizzle, UINT_32 pipeSwizzle,
UINT_64 baseAddr, ADDR_TILEINFO* pTileInfo) const;
UINT_32 ComputeSliceTileSwizzle(
AddrTileMode tileMode, UINT_32 baseSwizzle, UINT_32 slice, UINT_64 baseAddr,
ADDR_TILEINFO* pTileInfo) const;
/// Addressing functions
UINT_32 ComputeBankFromCoord(
UINT_32 x, UINT_32 y, UINT_32 slice,
AddrTileMode tileMode, UINT_32 bankSwizzle, UINT_32 tileSpitSlice,
ADDR_TILEINFO* pTileInfo) const;
UINT_32 ComputeBankFromAddr(
UINT_64 addr, UINT_32 numBanks, UINT_32 numPipes) const;
UINT_32 ComputePipeRotation(
AddrTileMode tileMode, UINT_32 numPipes) const;
UINT_32 ComputeBankRotation(
AddrTileMode tileMode, UINT_32 numBanks,
UINT_32 numPipes) const;
VOID ComputeSurfaceCoord2DFromBankPipe(
AddrTileMode tileMode, UINT_32 x, UINT_32 y, UINT_32 slice,
UINT_32 bank, UINT_32 pipe,
UINT_32 bankSwizzle, UINT_32 pipeSwizzle, UINT_32 tileSlices,
ADDR_TILEINFO* pTileInfo,
CoordFromBankPipe *pOutput) const;
/// Htile/Cmask functions
UINT_64 ComputeHtileBytes(
UINT_32 pitch, UINT_32 height, UINT_32 bpp,
BOOL_32 isLinear, UINT_32 numSlices, UINT_64* sliceBytes, UINT_32 baseAlign) const;
// Static functions
static BOOL_32 IsTileInfoAllZero(ADDR_TILEINFO* pTileInfo);
static UINT_32 ComputeFmaskNumPlanesFromNumSamples(UINT_32 numSamples);
static UINT_32 ComputeFmaskResolvedBppFromNumSamples(UINT_32 numSamples);
private:
BOOL_32 ComputeSurfaceInfoLinear(
const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut,
UINT_32 padDims) const;
BOOL_32 ComputeSurfaceInfoMicroTiled(
const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut,
UINT_32 padDims,
AddrTileMode expTileMode) const;
BOOL_32 ComputeSurfaceInfoMacroTiled(
const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut,
UINT_32 padDims,
AddrTileMode expTileMode) const;
BOOL_32 ComputeSurfaceAlignmentsLinear(
AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags,
UINT_32* pBaseAlign, UINT_32* pPitchAlign, UINT_32* pHeightAlign) const;
BOOL_32 ComputeSurfaceAlignmentsMicroTiled(
AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags, UINT_32 numSamples,
UINT_32* pBaseAlign, UINT_32* pPitchAlign, UINT_32* pHeightAlign) const;
BOOL_32 ComputeSurfaceAlignmentsMacroTiled(
AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags,
UINT_32 mipLevel, UINT_32 numSamples,
ADDR_TILEINFO* pTileInfo,
UINT_32* pBaseAlign, UINT_32* pPitchAlign, UINT_32* pHeightAlign) const;
/// Surface addressing functions
UINT_64 DispatchComputeSurfaceAddrFromCoord(
const ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const;
VOID DispatchComputeSurfaceCoordFromAddr(
const ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn,
ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut) const;
UINT_64 ComputeSurfaceAddrFromCoordMicroTiled(
UINT_32 x, UINT_32 y, UINT_32 slice, UINT_32 sample,
UINT_32 bpp, UINT_32 pitch, UINT_32 height, UINT_32 numSamples,
AddrTileMode tileMode,
AddrTileType microTileType, BOOL_32 isDepthSampleOrder,
UINT_32* pBitPosition) const;
UINT_64 ComputeSurfaceAddrFromCoordMacroTiled(
UINT_32 x, UINT_32 y, UINT_32 slice, UINT_32 sample,
UINT_32 bpp, UINT_32 pitch, UINT_32 height, UINT_32 numSamples,
AddrTileMode tileMode,
AddrTileType microTileType, BOOL_32 ignoreSE, BOOL_32 isDepthSampleOrder,
UINT_32 pipeSwizzle, UINT_32 bankSwizzle,
ADDR_TILEINFO* pTileInfo,
UINT_32* pBitPosition) const;
VOID ComputeSurfaceCoordFromAddrMacroTiled(
UINT_64 addr, UINT_32 bitPosition,
UINT_32 bpp, UINT_32 pitch, UINT_32 height, UINT_32 numSamples,
AddrTileMode tileMode, UINT_32 tileBase, UINT_32 compBits,
AddrTileType microTileType, BOOL_32 ignoreSE, BOOL_32 isDepthSampleOrder,
UINT_32 pipeSwizzle, UINT_32 bankSwizzle,
ADDR_TILEINFO* pTileInfo,
UINT_32* pX, UINT_32* pY, UINT_32* pSlice, UINT_32* pSample) const;
/// Fmask functions
UINT_64 DispatchComputeFmaskAddrFromCoord(
const ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT* pIn,
ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT* pOut) const;
VOID DispatchComputeFmaskCoordFromAddr(
const ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT* pIn,
ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT* pOut) const;
// FMASK related methods - private
UINT_64 ComputeFmaskAddrFromCoordMicroTiled(
UINT_32 x, UINT_32 y, UINT_32 slice, UINT_32 sample, UINT_32 plane,
UINT_32 pitch, UINT_32 height, UINT_32 numSamples, AddrTileMode tileMode,
BOOL_32 resolved, UINT_32* pBitPosition) const;
VOID ComputeFmaskCoordFromAddrMicroTiled(
UINT_64 addr, UINT_32 bitPosition,
UINT_32 pitch, UINT_32 height, UINT_32 numSamples,
AddrTileMode tileMode, BOOL_32 resolved,
UINT_32* pX, UINT_32* pY, UINT_32* pSlice, UINT_32* pSample, UINT_32* pPlane) const;
VOID ComputeFmaskCoordFromAddrMacroTiled(
UINT_64 addr, UINT_32 bitPosition,
UINT_32 pitch, UINT_32 height, UINT_32 numSamples, AddrTileMode tileMode,
UINT_32 pipeSwizzle, UINT_32 bankSwizzle,
BOOL_32 ignoreSE,
ADDR_TILEINFO* pTileInfo,
BOOL_32 resolved,
UINT_32* pX, UINT_32* pY, UINT_32* pSlice, UINT_32* pSample, UINT_32* pPlane) const;
UINT_64 ComputeFmaskAddrFromCoordMacroTiled(
UINT_32 x, UINT_32 y, UINT_32 slice, UINT_32 sample, UINT_32 plane,
UINT_32 pitch, UINT_32 height, UINT_32 numSamples,
AddrTileMode tileMode, UINT_32 pipeSwizzle, UINT_32 bankSwizzle,
BOOL_32 ignoreSE,
ADDR_TILEINFO* pTileInfo,
BOOL_32 resolved,
UINT_32* pBitPosition) const;
/// Sanity check functions
BOOL_32 SanityCheckMacroTiled(
ADDR_TILEINFO* pTileInfo) const;
protected:
UINT_32 m_ranks; ///< Number of ranks - MC_ARB_RAMCFG.NOOFRANK
UINT_32 m_logicalBanks; ///< Logical banks = m_banks * m_ranks if m_banks != 16
UINT_32 m_bankInterleave; ///< Bank interleave, as a multiple of pipe interleave size
};
#endif

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/*
* Copyright © 2014 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*/
/**
***************************************************************************************************
* @file siaddrlib.h
* @brief Contains the R800AddrLib class definition.
***************************************************************************************************
*/
#ifndef __SI_ADDR_LIB_H__
#define __SI_ADDR_LIB_H__
#include "addrlib.h"
#include "egbaddrlib.h"
/**
***************************************************************************************************
* @brief Describes the information in tile mode table
***************************************************************************************************
*/
struct ADDR_TILECONFIG
{
AddrTileMode mode;
AddrTileType type;
ADDR_TILEINFO info;
};
/**
***************************************************************************************************
* @brief SI specific settings structure.
***************************************************************************************************
*/
struct SIChipSettings
{
struct
{
UINT_32 isSouthernIsland : 1;
UINT_32 isTahiti : 1;
UINT_32 isPitCairn : 1;
UINT_32 isCapeVerde : 1;
/// Oland/Hainan are of GFXIP 6.0, similar with SI
UINT_32 isOland : 1;
UINT_32 isHainan : 1;
};
};
/**
***************************************************************************************************
* @brief This class is the SI specific address library
* function set.
***************************************************************************************************
*/
class SIAddrLib : public EgBasedAddrLib
{
public:
/// Creates SIAddrLib object
static AddrLib* CreateObj(const AddrClient* pClient)
{
return new(pClient) SIAddrLib(pClient);
}
protected:
SIAddrLib(const AddrClient* pClient);
virtual ~SIAddrLib();
// Hwl interface - defined in AddrLib
virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfo(
const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
virtual ADDR_E_RETURNCODE HwlConvertTileInfoToHW(
const ADDR_CONVERT_TILEINFOTOHW_INPUT* pIn,
ADDR_CONVERT_TILEINFOTOHW_OUTPUT* pOut) const;
virtual UINT_64 HwlComputeXmaskAddrFromCoord(
UINT_32 pitch, UINT_32 height, UINT_32 x, UINT_32 y, UINT_32 slice, UINT_32 numSlices,
UINT_32 factor, BOOL_32 isLinear, BOOL_32 isWidth8, BOOL_32 isHeight8,
ADDR_TILEINFO* pTileInfo, UINT_32* pBitPosition) const;
virtual VOID HwlComputeXmaskCoordFromAddr(
UINT_64 addr, UINT_32 bitPosition, UINT_32 pitch, UINT_32 height, UINT_32 numSlices,
UINT_32 factor, BOOL_32 isLinear, BOOL_32 isWidth8, BOOL_32 isHeight8,
ADDR_TILEINFO* pTileInfo, UINT_32* pX, UINT_32* pY, UINT_32* pSlice) const;
virtual ADDR_E_RETURNCODE HwlGetTileIndex(
const ADDR_GET_TILEINDEX_INPUT* pIn,
ADDR_GET_TILEINDEX_OUTPUT* pOut) const;
virtual BOOL_32 HwlComputeMipLevel(
ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn) const;
virtual AddrChipFamily HwlConvertChipFamily(
UINT_32 uChipFamily, UINT_32 uChipRevision);
virtual BOOL_32 HwlInitGlobalParams(
const ADDR_CREATE_INPUT* pCreateIn);
virtual ADDR_E_RETURNCODE HwlSetupTileCfg(
INT_32 index, INT_32 macroModeIndex,
ADDR_TILEINFO* pInfo, AddrTileMode* pMode = 0, AddrTileType* pType = 0) const;
virtual VOID HwlComputeTileDataWidthAndHeightLinear(
UINT_32* pMacroWidth, UINT_32* pMacroHeight,
UINT_32 bpp, ADDR_TILEINFO* pTileInfo) const;
virtual UINT_64 HwlComputeHtileBytes(
UINT_32 pitch, UINT_32 height, UINT_32 bpp,
BOOL_32 isLinear, UINT_32 numSlices, UINT_64* pSliceBytes, UINT_32 baseAlign) const;
virtual UINT_32 ComputePipeFromCoord(
UINT_32 x, UINT_32 y, UINT_32 slice,
AddrTileMode tileMode, UINT_32 pipeSwizzle, BOOL_32 ignoreSE,
ADDR_TILEINFO* pTileInfo) const;
virtual UINT_32 HwlGetPipes(const ADDR_TILEINFO* pTileInfo) const;
/// Pre-handler of 3x pitch (96 bit) adjustment
virtual UINT_32 HwlPreHandleBaseLvl3xPitch(
const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn, UINT_32 expPitch) const;
/// Post-handler of 3x pitch adjustment
virtual UINT_32 HwlPostHandleBaseLvl3xPitch(
const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn, UINT_32 expPitch) const;
/// Dummy function to finalize the inheritance
virtual UINT_32 HwlComputeXmaskCoordYFrom8Pipe(
UINT_32 pipe, UINT_32 x) const;
// Sub-hwl interface - defined in EgBasedAddrLib
virtual VOID HwlSetupTileInfo(
AddrTileMode tileMode, ADDR_SURFACE_FLAGS flags,
UINT_32 bpp, UINT_32 pitch, UINT_32 height, UINT_32 numSamples,
ADDR_TILEINFO* inputTileInfo, ADDR_TILEINFO* outputTileInfo,
AddrTileType inTileType, ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
virtual UINT_32 HwlGetPitchAlignmentMicroTiled(
AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags, UINT_32 numSamples) const;
virtual UINT_64 HwlGetSizeAdjustmentMicroTiled(
UINT_32 thickness, UINT_32 bpp, ADDR_SURFACE_FLAGS flags, UINT_32 numSamples,
UINT_32 baseAlign, UINT_32 pitchAlign,
UINT_32 *pPitch, UINT_32 *pHeight) const;
virtual VOID HwlCheckLastMacroTiledLvl(
const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn, ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
virtual BOOL_32 HwlTileInfoEqual(
const ADDR_TILEINFO* pLeft, const ADDR_TILEINFO* pRight) const;
virtual AddrTileMode HwlDegradeThickTileMode(
AddrTileMode baseTileMode, UINT_32 numSlices, UINT_32* pBytesPerTile) const;
virtual BOOL_32 HwlOverrideTileMode(
const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,
AddrTileMode* pTileMode,
AddrTileType* pTileType) const;
virtual BOOL_32 HwlSanityCheckMacroTiled(
ADDR_TILEINFO* pTileInfo) const
{
return TRUE;
}
virtual UINT_32 HwlGetPitchAlignmentLinear(UINT_32 bpp, ADDR_SURFACE_FLAGS flags) const;
virtual UINT_64 HwlGetSizeAdjustmentLinear(
AddrTileMode tileMode,
UINT_32 bpp, UINT_32 numSamples, UINT_32 baseAlign, UINT_32 pitchAlign,
UINT_32 *pPitch, UINT_32 *pHeight, UINT_32 *pHeightAlign) const;
virtual VOID HwlComputeSurfaceCoord2DFromBankPipe(
AddrTileMode tileMode, UINT_32* pX, UINT_32* pY, UINT_32 slice,
UINT_32 bank, UINT_32 pipe,
UINT_32 bankSwizzle, UINT_32 pipeSwizzle, UINT_32 tileSlices,
BOOL_32 ignoreSE,
ADDR_TILEINFO* pTileInfo) const;
virtual UINT_32 HwlPreAdjustBank(
UINT_32 tileX, UINT_32 bank, ADDR_TILEINFO* pTileInfo) const;
virtual INT_32 HwlPostCheckTileIndex(
const ADDR_TILEINFO* pInfo, AddrTileMode mode, AddrTileType type,
INT curIndex = TileIndexInvalid) const;
virtual VOID HwlFmaskPreThunkSurfInfo(
const ADDR_COMPUTE_FMASK_INFO_INPUT* pFmaskIn,
const ADDR_COMPUTE_FMASK_INFO_OUTPUT* pFmaskOut,
ADDR_COMPUTE_SURFACE_INFO_INPUT* pSurfIn,
ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pSurfOut) const;
virtual VOID HwlFmaskPostThunkSurfInfo(
const ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pSurfOut,
ADDR_COMPUTE_FMASK_INFO_OUTPUT* pFmaskOut) const;
virtual UINT_32 HwlComputeFmaskBits(
const ADDR_COMPUTE_FMASK_INFO_INPUT* pIn,
UINT_32* pNumSamples) const;
virtual BOOL_32 HwlReduceBankWidthHeight(
UINT_32 tileSize, UINT_32 bpp, ADDR_SURFACE_FLAGS flags, UINT_32 numSamples,
UINT_32 bankHeightAlign, UINT_32 pipes,
ADDR_TILEINFO* pTileInfo) const
{
return TRUE;
}
// Protected non-virtual functions
VOID ComputeTileCoordFromPipeAndElemIdx(
UINT_32 elemIdx, UINT_32 pipe, AddrPipeCfg pipeCfg, UINT_32 pitchInMacroTile,
UINT_32 x, UINT_32 y, UINT_32* pX, UINT_32* pY) const;
UINT_32 TileCoordToMaskElementIndex(
UINT_32 tx, UINT_32 ty, AddrPipeCfg pipeConfig,
UINT_32 *macroShift, UINT_32 *elemIdxBits) const;
BOOL_32 DecodeGbRegs(
const ADDR_REGISTER_VALUE* pRegValue);
const ADDR_TILECONFIG* GetTileSetting(
UINT_32 index) const;
static const UINT_32 TileTableSize = 32;
ADDR_TILECONFIG m_tileTable[TileTableSize];
UINT_32 m_noOfEntries;
private:
UINT_32 GetPipePerSurf(AddrPipeCfg pipeConfig) const;
VOID ReadGbTileMode(
UINT_32 regValue, ADDR_TILECONFIG* pCfg) const;
BOOL_32 InitTileSettingTable(
const UINT_32 *pSetting, UINT_32 noOfEntries);
SIChipSettings m_settings;
};
#endif

5
src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
View file

@ -486,10 +486,11 @@ static void amdgpu_bo_set_tiling(struct pb_buffer *_buf,
struct radeon_winsys_cs *rcs,
enum radeon_bo_layout microtiled,
enum radeon_bo_layout macrotiled,
unsigned pipe_config,
unsigned bankw, unsigned bankh,
unsigned tile_split,
unsigned stencil_tile_split,
unsigned mtilea,
unsigned mtilea, unsigned num_banks,
uint32_t pitch,
bool scanout)
{
@ -504,11 +505,13 @@ static void amdgpu_bo_set_tiling(struct pb_buffer *_buf,
else
tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 1); /* LINEAR_ALIGNED */
tiling_flags |= AMDGPU_TILING_SET(PIPE_CONFIG, pipe_config);
tiling_flags |= AMDGPU_TILING_SET(BANK_WIDTH, util_logbase2(bankw));
tiling_flags |= AMDGPU_TILING_SET(BANK_HEIGHT, util_logbase2(bankh));
if (tile_split)
tiling_flags |= AMDGPU_TILING_SET(TILE_SPLIT, eg_tile_split_rev(tile_split));
tiling_flags |= AMDGPU_TILING_SET(MACRO_TILE_ASPECT, util_logbase2(mtilea));
tiling_flags |= AMDGPU_TILING_SET(NUM_BANKS, util_logbase2(num_banks)-1);
if (scanout)
tiling_flags |= AMDGPU_TILING_SET(MICRO_TILE_MODE, 0); /* DISPLAY_MICRO_TILING */

157
src/gallium/winsys/amdgpu/drm/amdgpu_id.h Normal file
View file

@ -0,0 +1,157 @@
/*
* Copyright © 2014 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*/
/**
* This file is included by addrlib. It adds GPU family definitions and
* macros compatible with addrlib.
*/
#ifndef AMDGPU_ID_H
#define AMDGPU_ID_H
#include "pipe/p_config.h"
#if defined(PIPE_ARCH_LITTLE_ENDIAN)
#define LITTLEENDIAN_CPU
#elif defined(PIPE_ARCH_BIG_ENDIAN)
#define BIGENDIAN_CPU
#endif
enum {
FAMILY_UNKNOWN,
FAMILY_SI,
FAMILY_CI,
FAMILY_KV,
FAMILY_VI,
FAMILY_CZ,
FAMILY_PI,
FAMILY_LAST,
};
/* SI specific rev IDs */
enum {
SI_TAHITI_P_A11 = 1,
SI_TAHITI_P_A0 = SI_TAHITI_P_A11, /*A0 is alias of A11*/
SI_TAHITI_P_A21 = 5,
SI_TAHITI_P_B0 = SI_TAHITI_P_A21, /*B0 is alias of A21*/
SI_TAHITI_P_A22 = 6,
SI_TAHITI_P_B1 = SI_TAHITI_P_A22, /*B1 is alias of A22*/
SI_PITCAIRN_PM_A11 = 20,
SI_PITCAIRN_PM_A0 = SI_PITCAIRN_PM_A11, /*A0 is alias of A11*/
SI_PITCAIRN_PM_A12 = 21,
SI_PITCAIRN_PM_A1 = SI_PITCAIRN_PM_A12, /*A1 is alias of A12*/
SI_CAPEVERDE_M_A11 = 40,
SI_CAPEVERDE_M_A0 = SI_CAPEVERDE_M_A11, /*A0 is alias of A11*/
SI_CAPEVERDE_M_A12 = 41,
SI_CAPEVERDE_M_A1 = SI_CAPEVERDE_M_A12, /*A1 is alias of A12*/
SI_OLAND_M_A0 = 60,
SI_HAINAN_V_A0 = 70,
SI_UNKNOWN = 0xFF
};
#define ASICREV_IS_TAHITI_P(eChipRev) \
(eChipRev < SI_PITCAIRN_PM_A11)
#define ASICREV_IS_PITCAIRN_PM(eChipRev) \
((eChipRev >= SI_PITCAIRN_PM_A11) && (eChipRev < SI_CAPEVERDE_M_A11))
#define ASICREV_IS_CAPEVERDE_M(eChipRev) \
((eChipRev >= SI_CAPEVERDE_M_A11) && (eChipRev < SI_OLAND_M_A0))
#define ASICREV_IS_OLAND_M(eChipRev) \
((eChipRev >= SI_OLAND_M_A0) && (eChipRev < SI_HAINAN_V_A0))
#define ASICREV_IS_HAINAN_V(eChipRev) \
(eChipRev >= SI_HAINAN_V_A0)
/* CI specific revIDs */
enum {
CI_BONAIRE_M_A0 = 20,
CI_BONAIRE_M_A1 = 21,
CI_HAWAII_P_A0 = 40,
CI_UNKNOWN = 0xFF
};
#define ASICREV_IS_BONAIRE_M(eChipRev) \
((eChipRev >= CI_BONAIRE_M_A0) && (eChipRev < CI_HAWAII_P_A0))
#define ASICREV_IS_HAWAII_P(eChipRev) \
(eChipRev >= CI_HAWAII_P_A0)
/* KV specific rev IDs */
enum {
KV_SPECTRE_A0 = 0x01, /* KV1 with Spectre GFX core, 8-8-1-2 (CU-Pix-Primitive-RB) */
KV_SPOOKY_A0 = 0x41, /* KV2 with Spooky GFX core, including downgraded from Spectre core, 3-4-1-1 (CU-Pix-Primitive-RB) */
KB_KALINDI_A0 = 0x81, /* KB with Kalindi GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
KB_KALINDI_A1 = 0x82, /* KB with Kalindi GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
BV_KALINDI_A2 = 0x85, /* BV with Kalindi GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
ML_GODAVARI_A0 = 0xa1, /* ML with Godavari GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
ML_GODAVARI_A1 = 0xa2, /* ML with Godavari GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
KV_UNKNOWN = 0xFF
};
#define ASICREV_IS_SPECTRE(eChipRev) \
((eChipRev >= KV_SPECTRE_A0) && (eChipRev < KV_SPOOKY_A0)) /* identify all versions of SPRECTRE and supported features set */
#define ASICREV_IS_SPOOKY(eChipRev) \
((eChipRev >= KV_SPOOKY_A0) && (eChipRev < KB_KALINDI_A0)) /* identify all versions of SPOOKY and supported features set */
#define ASICREV_IS_KALINDI(eChipRev) \
((eChipRev >= KB_KALINDI_A0) && (eChipRev < KV_UNKNOWN)) /* identify all versions of KALINDI and supported features set */
/* Following macros are subset of ASICREV_IS_KALINDI macro */
#define ASICREV_IS_KALINDI_BHAVANI(eChipRev) \
((eChipRev >= BV_KALINDI_A2) && (eChipRev < ML_GODAVARI_A0)) /* identify all versions of BHAVANI and supported features set */
#define ASICREV_IS_KALINDI_GODAVARI(eChipRev) \
((eChipRev >= ML_GODAVARI_A0) && (eChipRev < KV_UNKNOWN)) /* identify all versions of GODAVARI and supported features set */
/* VI specific rev IDs */
enum {
VI_ICELAND_M_A0 = 1,
VI_TONGA_P_A0 = 20,
VI_TONGA_P_A1 = 21,
VI_UNKNOWN = 0xFF
};
#define ASICREV_IS_ICELAND_M(eChipRev) \
(eChipRev < VI_TONGA_P_A0)
#define ASICREV_IS_TONGA_P(eChipRev) \
(eChipRev >= VI_TONGA_P_A0)
/* CZ specific rev IDs */
enum {
CZ_CARRIZO_A0 = 0x01,
CZ_UNKNOWN = 0xFF
};
#define ASICREV_IS_CARRIZO(eChipRev) \
(eChipRev >= CARRIZO_A0)
#endif /* AMDGPU_ID_H */

438
src/gallium/winsys/amdgpu/drm/amdgpu_surface.c Normal file
View file

@ -0,0 +1,438 @@
/*
* Copyright © 2011 Red Hat All Rights Reserved.
* Copyright © 2014 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*/
/* Contact:
* Marek Olšák <maraeo@gmail.com>
*/
#include "amdgpu_winsys.h"
#ifndef NO_ENTRIES
#define NO_ENTRIES 32
#endif
#ifndef NO_MACRO_ENTRIES
#define NO_MACRO_ENTRIES 16
#endif
#ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
#define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
#endif
static int amdgpu_surface_sanity(const struct radeon_surf *surf)
{
unsigned type = RADEON_SURF_GET(surf->flags, TYPE);
if (!(surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX))
return -EINVAL;
/* all dimension must be at least 1 ! */
if (!surf->npix_x || !surf->npix_y || !surf->npix_z ||
!surf->array_size)
return -EINVAL;
if (!surf->blk_w || !surf->blk_h || !surf->blk_d)
return -EINVAL;
switch (surf->nsamples) {
case 1:
case 2:
case 4:
case 8:
break;
default:
return -EINVAL;
}
switch (type) {
case RADEON_SURF_TYPE_1D:
if (surf->npix_y > 1)
return -EINVAL;
/* fall through */
case RADEON_SURF_TYPE_2D:
case RADEON_SURF_TYPE_CUBEMAP:
if (surf->npix_z > 1 || surf->array_size > 1)
return -EINVAL;
break;
case RADEON_SURF_TYPE_3D:
if (surf->array_size > 1)
return -EINVAL;
break;
case RADEON_SURF_TYPE_1D_ARRAY:
if (surf->npix_y > 1)
return -EINVAL;
/* fall through */
case RADEON_SURF_TYPE_2D_ARRAY:
if (surf->npix_z > 1)
return -EINVAL;
break;
default:
return -EINVAL;
}
return 0;
}
static void *ADDR_API allocSysMem(const ADDR_ALLOCSYSMEM_INPUT * pInput)
{
return malloc(pInput->sizeInBytes);
}
static ADDR_E_RETURNCODE ADDR_API freeSysMem(const ADDR_FREESYSMEM_INPUT * pInput)
{
free(pInput->pVirtAddr);
return ADDR_OK;
}
/**
* This returns the number of banks for the surface.
* Possible values: 2, 4, 8, 16.
*/
static uint32_t cik_num_banks(struct amdgpu_winsys *ws,
struct radeon_surf *surf)
{
unsigned index, tileb;
tileb = 8 * 8 * surf->bpe;
tileb = MIN2(surf->tile_split, tileb);
for (index = 0; tileb > 64; index++) {
tileb >>= 1;
}
assert(index < 16);
return 2 << ((ws->amdinfo.gb_macro_tile_mode[index] >> 6) & 0x3);
}
ADDR_HANDLE amdgpu_addr_create(struct amdgpu_winsys *ws)
{
ADDR_CREATE_INPUT addrCreateInput = {0};
ADDR_CREATE_OUTPUT addrCreateOutput = {0};
ADDR_REGISTER_VALUE regValue = {0};
ADDR_CREATE_FLAGS createFlags = {{0}};
ADDR_E_RETURNCODE addrRet;
addrCreateInput.size = sizeof(ADDR_CREATE_INPUT);
addrCreateOutput.size = sizeof(ADDR_CREATE_OUTPUT);
regValue.noOfBanks = ws->amdinfo.mc_arb_ramcfg & 0x3;
regValue.gbAddrConfig = ws->amdinfo.gb_addr_cfg;
regValue.noOfRanks = (ws->amdinfo.mc_arb_ramcfg & 0x4) >> 2;
regValue.backendDisables = ws->amdinfo.backend_disable[0];
regValue.pTileConfig = ws->amdinfo.gb_tile_mode;
regValue.noOfEntries = sizeof(ws->amdinfo.gb_tile_mode) /
sizeof(ws->amdinfo.gb_tile_mode[0]);
regValue.pMacroTileConfig = ws->amdinfo.gb_macro_tile_mode;
regValue.noOfMacroEntries = sizeof(ws->amdinfo.gb_macro_tile_mode) /
sizeof(ws->amdinfo.gb_macro_tile_mode[0]);
createFlags.value = 0;
createFlags.useTileIndex = 1;
createFlags.degradeBaseLevel = 1;
addrCreateInput.chipEngine = CIASICIDGFXENGINE_SOUTHERNISLAND;
addrCreateInput.chipFamily = ws->family;
addrCreateInput.chipRevision = ws->rev_id;
addrCreateInput.createFlags = createFlags;
addrCreateInput.callbacks.allocSysMem = allocSysMem;
addrCreateInput.callbacks.freeSysMem = freeSysMem;
addrCreateInput.callbacks.debugPrint = 0;
addrCreateInput.regValue = regValue;
addrRet = AddrCreate(&addrCreateInput, &addrCreateOutput);
if (addrRet != ADDR_OK)
return NULL;
return addrCreateOutput.hLib;
}
static int compute_level(struct amdgpu_winsys *ws,
struct radeon_surf *surf, bool is_stencil,
unsigned level, unsigned type, bool compressed,
ADDR_COMPUTE_SURFACE_INFO_INPUT *AddrSurfInfoIn,
ADDR_COMPUTE_SURFACE_INFO_OUTPUT *AddrSurfInfoOut)
{
struct radeon_surf_level *surf_level;
ADDR_E_RETURNCODE ret;
AddrSurfInfoIn->mipLevel = level;
AddrSurfInfoIn->width = u_minify(surf->npix_x, level);
AddrSurfInfoIn->height = u_minify(surf->npix_y, level);
if (type == RADEON_SURF_TYPE_3D)
AddrSurfInfoIn->numSlices = u_minify(surf->npix_z, level);
else if (type == RADEON_SURF_TYPE_CUBEMAP)
AddrSurfInfoIn->numSlices = 6;
else
AddrSurfInfoIn->numSlices = surf->array_size;
if (level > 0) {
/* Set the base level pitch. This is needed for calculation
* of non-zero levels. */
if (is_stencil)
AddrSurfInfoIn->basePitch = surf->stencil_level[0].nblk_x;
else
AddrSurfInfoIn->basePitch = surf->level[0].nblk_x;
/* Convert blocks to pixels for compressed formats. */
if (compressed)
AddrSurfInfoIn->basePitch *= surf->blk_w;
}
ret = AddrComputeSurfaceInfo(ws->addrlib,
AddrSurfInfoIn,
AddrSurfInfoOut);
if (ret != ADDR_OK) {
return ret;
}
surf_level = is_stencil ? &surf->stencil_level[level] : &surf->level[level];
surf_level->offset = align(surf->bo_size, AddrSurfInfoOut->baseAlign);
surf_level->slice_size = AddrSurfInfoOut->sliceSize;
surf_level->pitch_bytes = AddrSurfInfoOut->pitch * (is_stencil ? 1 : surf->bpe);
surf_level->npix_x = u_minify(surf->npix_x, level);
surf_level->npix_y = u_minify(surf->npix_y, level);
surf_level->npix_z = u_minify(surf->npix_z, level);
surf_level->nblk_x = AddrSurfInfoOut->pitch;
surf_level->nblk_y = AddrSurfInfoOut->height;
if (type == RADEON_SURF_TYPE_3D)
surf_level->nblk_z = AddrSurfInfoOut->depth;
else
surf_level->nblk_z = 1;
switch (AddrSurfInfoOut->tileMode) {
case ADDR_TM_LINEAR_GENERAL:
surf_level->mode = RADEON_SURF_MODE_LINEAR;
break;
case ADDR_TM_LINEAR_ALIGNED:
surf_level->mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
break;
case ADDR_TM_1D_TILED_THIN1:
surf_level->mode = RADEON_SURF_MODE_1D;
break;
case ADDR_TM_2D_TILED_THIN1:
surf_level->mode = RADEON_SURF_MODE_2D;
break;
default:
assert(0);
}
if (is_stencil)
surf->stencil_tiling_index[level] = AddrSurfInfoOut->tileIndex;
else
surf->tiling_index[level] = AddrSurfInfoOut->tileIndex;
surf->bo_size = surf_level->offset + AddrSurfInfoOut->surfSize;
return 0;
}
static int amdgpu_surface_init(struct radeon_winsys *rws,
struct radeon_surf *surf)
{
struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
unsigned level, mode, type;
bool compressed;
ADDR_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
ADDR_COMPUTE_SURFACE_INFO_OUTPUT AddrSurfInfoOut = {0};
ADDR_TILEINFO AddrTileInfoIn = {0};
ADDR_TILEINFO AddrTileInfoOut = {0};
int r;
r = amdgpu_surface_sanity(surf);
if (r)
return r;
AddrSurfInfoIn.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_INPUT);
AddrSurfInfoOut.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_OUTPUT);
AddrSurfInfoOut.pTileInfo = &AddrTileInfoOut;
type = RADEON_SURF_GET(surf->flags, TYPE);
mode = RADEON_SURF_GET(surf->flags, MODE);
compressed = surf->blk_w == 4 && surf->blk_h == 4;
/* MSAA and FMASK require 2D tiling. */
if (surf->nsamples > 1 ||
(surf->flags & RADEON_SURF_FMASK))
mode = RADEON_SURF_MODE_2D;
/* DB doesn't support linear layouts. */
if (surf->flags & (RADEON_SURF_Z_OR_SBUFFER) &&
mode < RADEON_SURF_MODE_1D)
mode = RADEON_SURF_MODE_1D;
/* Set the requested tiling mode. */
switch (mode) {
case RADEON_SURF_MODE_LINEAR:
AddrSurfInfoIn.tileMode = ADDR_TM_LINEAR_GENERAL;
break;
case RADEON_SURF_MODE_LINEAR_ALIGNED:
AddrSurfInfoIn.tileMode = ADDR_TM_LINEAR_ALIGNED;
break;
case RADEON_SURF_MODE_1D:
AddrSurfInfoIn.tileMode = ADDR_TM_1D_TILED_THIN1;
break;
case RADEON_SURF_MODE_2D:
AddrSurfInfoIn.tileMode = ADDR_TM_2D_TILED_THIN1;
break;
default:
assert(0);
}
/* The format must be set correctly for the allocation of compressed
* textures to work. In other cases, setting the bpp is sufficient. */
if (compressed) {
switch (surf->bpe) {
case 8:
AddrSurfInfoIn.format = ADDR_FMT_BC1;
break;
case 16:
AddrSurfInfoIn.format = ADDR_FMT_BC3;
break;
default:
assert(0);
}
}
else {
AddrSurfInfoIn.bpp = surf->bpe * 8;
}
AddrSurfInfoIn.numSamples = surf->nsamples;
AddrSurfInfoIn.tileIndex = -1;
/* Set the micro tile type. */
if (surf->flags & RADEON_SURF_SCANOUT)
AddrSurfInfoIn.tileType = ADDR_DISPLAYABLE;
else if (surf->flags & RADEON_SURF_Z_OR_SBUFFER)
AddrSurfInfoIn.tileType = ADDR_DEPTH_SAMPLE_ORDER;
else
AddrSurfInfoIn.tileType = ADDR_NON_DISPLAYABLE;
AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
AddrSurfInfoIn.flags.stencil = (surf->flags & RADEON_SURF_SBUFFER) != 0;
AddrSurfInfoIn.flags.cube = type == RADEON_SURF_TYPE_CUBEMAP;
AddrSurfInfoIn.flags.display = (surf->flags & RADEON_SURF_SCANOUT) != 0;
AddrSurfInfoIn.flags.pow2Pad = surf->last_level > 0;
AddrSurfInfoIn.flags.degrade4Space = 1;
/* This disables incorrect calculations (hacks) in addrlib. */
AddrSurfInfoIn.flags.noStencil = 1;
/* Set preferred macrotile parameters. This is usually required
* for shared resources. This is for 2D tiling only. */
if (AddrSurfInfoIn.tileMode >= ADDR_TM_2D_TILED_THIN1 &&
surf->bankw && surf->bankh && surf->mtilea && surf->tile_split) {
/* If any of these parameters are incorrect, the calculation
* will fail. */
AddrTileInfoIn.banks = cik_num_banks(ws, surf);
AddrTileInfoIn.bankWidth = surf->bankw;
AddrTileInfoIn.bankHeight = surf->bankh;
AddrTileInfoIn.macroAspectRatio = surf->mtilea;
AddrTileInfoIn.tileSplitBytes = surf->tile_split;
AddrSurfInfoIn.flags.degrade4Space = 0;
AddrSurfInfoIn.pTileInfo = &AddrTileInfoIn;
/* If AddrSurfInfoIn.pTileInfo is set, Addrlib doesn't set
* the tile index, because we are expected to know it if
* we know the other parameters.
*
* This is something that can easily be fixed in Addrlib.
* For now, just figure it out here.
* Note that only 2D_TILE_THIN1 is handled here.
*/
assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
assert(AddrSurfInfoIn.tileMode == ADDR_TM_2D_TILED_THIN1);
if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE)
AddrSurfInfoIn.tileIndex = 10; /* 2D displayable */
else
AddrSurfInfoIn.tileIndex = 14; /* 2D non-displayable */
}
surf->bo_size = 0;
/* Calculate texture layout information. */
for (level = 0; level <= surf->last_level; level++) {
r = compute_level(ws, surf, false, level, type, compressed,
&AddrSurfInfoIn, &AddrSurfInfoOut);
if (r)
return r;
if (level == 0) {
surf->bo_alignment = AddrSurfInfoOut.baseAlign;
surf->pipe_config = AddrSurfInfoOut.pTileInfo->pipeConfig - 1;
/* For 2D modes only. */
if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) {
surf->bankw = AddrSurfInfoOut.pTileInfo->bankWidth;
surf->bankh = AddrSurfInfoOut.pTileInfo->bankHeight;
surf->mtilea = AddrSurfInfoOut.pTileInfo->macroAspectRatio;
surf->tile_split = AddrSurfInfoOut.pTileInfo->tileSplitBytes;
surf->num_banks = AddrSurfInfoOut.pTileInfo->banks;
}
}
}
/* Calculate texture layout information for stencil. */
if (surf->flags & RADEON_SURF_SBUFFER) {
AddrSurfInfoIn.bpp = 8;
/* This will be ignored if AddrSurfInfoIn.pTileInfo is NULL. */
AddrTileInfoIn.tileSplitBytes = surf->stencil_tile_split;
for (level = 0; level <= surf->last_level; level++) {
r = compute_level(ws, surf, true, level, type, compressed,
&AddrSurfInfoIn, &AddrSurfInfoOut);
if (r)
return r;
if (level == 0) {
surf->stencil_offset = surf->stencil_level[0].offset;
/* For 2D modes only. */
if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) {
surf->stencil_tile_split =
AddrSurfInfoOut.pTileInfo->tileSplitBytes;
}
}
}
}
return 0;
}
static int amdgpu_surface_best(struct radeon_winsys *rws,
struct radeon_surf *surf)
{
return 0;
}
void amdgpu_surface_init_functions(struct amdgpu_winsys *ws)
{
ws->base.surface_init = amdgpu_surface_init;
ws->base.surface_best = amdgpu_surface_best;
}

50
src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
View file

@ -39,6 +39,7 @@
#include <xf86drm.h>
#include <stdio.h>
#include <sys/stat.h>
#include "amdgpu_id.h"
#define CIK_TILE_MODE_COLOR_2D 14
@ -192,6 +193,51 @@ static boolean do_winsys_init(struct amdgpu_winsys *ws)
goto fail;
}
/* family and rev_id are for addrlib */
switch (ws->info.family) {
case CHIP_BONAIRE:
ws->family = FAMILY_CI;
ws->rev_id = CI_BONAIRE_M_A0;
break;
case CHIP_KAVERI:
ws->family = FAMILY_KV;
ws->rev_id = KV_SPECTRE_A0;
break;
case CHIP_KABINI:
ws->family = FAMILY_KV;
ws->rev_id = KB_KALINDI_A0;
break;
case CHIP_HAWAII:
ws->family = FAMILY_CI;
ws->rev_id = CI_HAWAII_P_A0;
break;
case CHIP_MULLINS:
ws->family = FAMILY_KV;
ws->rev_id = ML_GODAVARI_A0;
break;
case CHIP_TONGA:
ws->family = FAMILY_VI;
ws->rev_id = VI_TONGA_P_A0;
break;
case CHIP_ICELAND:
ws->family = FAMILY_VI;
ws->rev_id = VI_ICELAND_M_A0;
break;
case CHIP_CARRIZO:
ws->family = FAMILY_CZ;
ws->rev_id = CZ_CARRIZO_A0;
break;
default:
fprintf(stderr, "amdgpu: Unknown family.\n");
goto fail;
}
ws->addrlib = amdgpu_addr_create(ws);
if (!ws->addrlib) {
fprintf(stderr, "amdgpu: Cannot create addrlib.\n");
goto fail;
}
/* Set hardware information. */
ws->info.gart_size = gtt.heap_size;
ws->info.vram_size = vram.heap_size;
@ -226,6 +272,8 @@ static boolean do_winsys_init(struct amdgpu_winsys *ws)
return TRUE;
fail:
if (ws->addrlib)
AddrDestroy(ws->addrlib);
amdgpu_device_deinitialize(ws->dev);
ws->dev = NULL;
return FALSE;
@ -239,6 +287,7 @@ static void amdgpu_winsys_destroy(struct radeon_winsys *rws)
ws->cman->destroy(ws->cman);
ws->kman->destroy(ws->kman);
AddrDestroy(ws->addrlib);
amdgpu_device_deinitialize(ws->dev);
FREE(rws);
@ -413,6 +462,7 @@ amdgpu_winsys_create(int fd, radeon_screen_create_t screen_create)
amdgpu_bomgr_init_functions(ws);
amdgpu_cs_init_functions(ws);
amdgpu_surface_init_functions(ws);
pipe_mutex_init(ws->bo_fence_lock);

7
src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h
View file

@ -33,6 +33,7 @@
#define AMDGPU_WINSYS_H
#include "gallium/drivers/radeon/radeon_winsys.h"
#include "addrlib/addrinterface.h"
#include "os/os_thread.h"
#include <amdgpu.h>
@ -60,6 +61,9 @@ struct amdgpu_winsys {
struct pb_manager *cman;
struct amdgpu_gpu_info amdinfo;
ADDR_HANDLE addrlib;
uint32_t rev_id;
unsigned family;
};
static inline struct amdgpu_winsys *
@ -68,4 +72,7 @@ amdgpu_winsys(struct radeon_winsys *base)
return (struct amdgpu_winsys*)base;
}
void amdgpu_surface_init_functions(struct amdgpu_winsys *ws);
ADDR_HANDLE amdgpu_addr_create(struct amdgpu_winsys *ws);
#endif

3
src/gallium/winsys/radeon/drm/radeon_drm_bo.c
View file

@ -774,10 +774,11 @@ static void radeon_bo_set_tiling(struct pb_buffer *_buf,
struct radeon_winsys_cs *rcs,
enum radeon_bo_layout microtiled,
enum radeon_bo_layout macrotiled,
unsigned pipe_config,
unsigned bankw, unsigned bankh,
unsigned tile_split,
unsigned stencil_tile_split,
unsigned mtilea,
unsigned mtilea, unsigned num_banks,
uint32_t pitch,
bool scanout)
{