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intel: Rename GENx keyword to GFXx

Browse source 
Commands used to do the changes:
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
grep -E "GEN[[:digit:]]+" -rIl $SEARCH_PATH | xargs sed -ie "s/GEN\([[:digit:]]\+\)/GFX\1/g"

Exclude the changes to modifiers:
grep -E "I915_.*GFX" -rIl $SEARCH_PATH | xargs sed -ie "s/\(I915_.*\)GFX/\1GEN/g"

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9936>
This commit is contained in:
Anuj Phogat 2021-03-29 16:02:30 -07:00 • committed by Marge Bot
parent 1d296484b4
commit e7e55af4d6
42 changed files with 239 additions and 239 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
src/gallium/drivers/iris/iris_blit.c
View file

@ -572,7 +572,7 @@ get_copy_region_aux_settings(struct iris_context *ice,
case ISL_AUX_USAGE_MCS: case ISL_AUX_USAGE_MCS:
case ISL_AUX_USAGE_MCS_CCS: case ISL_AUX_USAGE_MCS_CCS:
case ISL_AUX_USAGE_CCS_E: case ISL_AUX_USAGE_CCS_E:
case ISL_AUX_USAGE_GEN12_CCS_E: case ISL_AUX_USAGE_GFX12_CCS_E:
*out_aux_usage = res->aux.usage; *out_aux_usage = res->aux.usage;
/* blorp_copy may reinterpret the surface format and has limited support /* blorp_copy may reinterpret the surface format and has limited support

2
src/gallium/drivers/iris/iris_clear.c
View file

@ -134,7 +134,7 @@ can_fast_clear_color(struct iris_context *ice,
* to avoid stomping on other LODs. * to avoid stomping on other LODs.
*/ */
if (level > 0 && util_format_get_blocksizebits(p_res->format) == 8 && if (level > 0 && util_format_get_blocksizebits(p_res->format) == 8 &&
res->aux.usage == ISL_AUX_USAGE_GEN12_CCS_E && p_res->width0 % 64) { res->aux.usage == ISL_AUX_USAGE_GFX12_CCS_E && p_res->width0 % 64) {
return false; return false;
} }

10
src/gallium/drivers/iris/iris_resolve.c
View file

@ -55,7 +55,7 @@ disable_rb_aux_buffer(struct iris_context *ice,
/* We only need to worry about color compression and fast clears. */ /* We only need to worry about color compression and fast clears. */
if (tex_res->aux.usage != ISL_AUX_USAGE_CCS_D && if (tex_res->aux.usage != ISL_AUX_USAGE_CCS_D &&
tex_res->aux.usage != ISL_AUX_USAGE_CCS_E && tex_res->aux.usage != ISL_AUX_USAGE_CCS_E &&
tex_res->aux.usage != ISL_AUX_USAGE_GEN12_CCS_E) tex_res->aux.usage != ISL_AUX_USAGE_GFX12_CCS_E)
return false; return false;
for (unsigned i = 0; i < cso_fb->nr_cbufs; i++) { for (unsigned i = 0; i < cso_fb->nr_cbufs; i++) {
@ -839,7 +839,7 @@ iris_resource_texture_aux_usage(struct iris_context *ice,
return res->aux.usage; return res->aux.usage;
case ISL_AUX_USAGE_CCS_E: case ISL_AUX_USAGE_CCS_E:
case ISL_AUX_USAGE_GEN12_CCS_E: case ISL_AUX_USAGE_GFX12_CCS_E:
/* If we don't have any unresolved color, report an aux usage of /* If we don't have any unresolved color, report an aux usage of
* ISL_AUX_USAGE_NONE. This way, texturing won't even look at the * ISL_AUX_USAGE_NONE. This way, texturing won't even look at the
* aux surface and we can save some bandwidth. * aux surface and we can save some bandwidth.
@ -888,8 +888,8 @@ iris_image_view_aux_usage(struct iris_context *ice,
bool uses_atomic_load_store = bool uses_atomic_load_store =
ice->shaders.uncompiled[info->stage]->uses_atomic_load_store; ice->shaders.uncompiled[info->stage]->uses_atomic_load_store;
if (aux_usage == ISL_AUX_USAGE_GEN12_CCS_E && !uses_atomic_load_store) if (aux_usage == ISL_AUX_USAGE_GFX12_CCS_E && !uses_atomic_load_store)
return ISL_AUX_USAGE_GEN12_CCS_E; return ISL_AUX_USAGE_GFX12_CCS_E;
return ISL_AUX_USAGE_NONE; return ISL_AUX_USAGE_NONE;
} }
@ -984,7 +984,7 @@ iris_resource_render_aux_usage(struct iris_context *ice,
case ISL_AUX_USAGE_CCS_D: case ISL_AUX_USAGE_CCS_D:
case ISL_AUX_USAGE_CCS_E: case ISL_AUX_USAGE_CCS_E:
case ISL_AUX_USAGE_GEN12_CCS_E: case ISL_AUX_USAGE_GFX12_CCS_E:
/* Disable CCS for some cases of texture-view rendering. On gfx12, HW /* Disable CCS for some cases of texture-view rendering. On gfx12, HW
* may convert some subregions of shader output to fast-cleared blocks * may convert some subregions of shader output to fast-cleared blocks
* if CCS is enabled and the shader output matches the clear color. * if CCS is enabled and the shader output matches the clear color.

20
src/gallium/drivers/iris/iris_resource.c
View file

@ -59,7 +59,7 @@ enum modifier_priority {
MODIFIER_PRIORITY_X, MODIFIER_PRIORITY_X,
MODIFIER_PRIORITY_Y, MODIFIER_PRIORITY_Y,
MODIFIER_PRIORITY_Y_CCS, MODIFIER_PRIORITY_Y_CCS,
MODIFIER_PRIORITY_Y_GEN12_RC_CCS, MODIFIER_PRIORITY_Y_GFX12_RC_CCS,
}; };
static const uint64_t priority_to_modifier[] = { static const uint64_t priority_to_modifier[] = {
@ -68,7 +68,7 @@ static const uint64_t priority_to_modifier[] = {
[MODIFIER_PRIORITY_X] = I915_FORMAT_MOD_X_TILED, [MODIFIER_PRIORITY_X] = I915_FORMAT_MOD_X_TILED,
[MODIFIER_PRIORITY_Y] = I915_FORMAT_MOD_Y_TILED, [MODIFIER_PRIORITY_Y] = I915_FORMAT_MOD_Y_TILED,
[MODIFIER_PRIORITY_Y_CCS] = I915_FORMAT_MOD_Y_TILED_CCS, [MODIFIER_PRIORITY_Y_CCS] = I915_FORMAT_MOD_Y_TILED_CCS,
[MODIFIER_PRIORITY_Y_GEN12_RC_CCS] = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS, [MODIFIER_PRIORITY_Y_GFX12_RC_CCS] = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
}; };
static bool static bool
@ -145,7 +145,7 @@ select_best_modifier(struct gen_device_info *devinfo, enum pipe_format pfmt,
switch (modifiers[i]) { switch (modifiers[i]) {
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
prio = MAX2(prio, MODIFIER_PRIORITY_Y_GEN12_RC_CCS); prio = MAX2(prio, MODIFIER_PRIORITY_Y_GFX12_RC_CCS);
break; break;
case I915_FORMAT_MOD_Y_TILED_CCS: case I915_FORMAT_MOD_Y_TILED_CCS:
prio = MAX2(prio, MODIFIER_PRIORITY_Y_CCS); prio = MAX2(prio, MODIFIER_PRIORITY_Y_CCS);
@ -355,18 +355,18 @@ iris_get_isl_dim_layout(const struct gen_device_info *devinfo,
case PIPE_TEXTURE_1D: case PIPE_TEXTURE_1D:
case PIPE_TEXTURE_1D_ARRAY: case PIPE_TEXTURE_1D_ARRAY:
return (devinfo->ver >= 9 && tiling == ISL_TILING_LINEAR ? return (devinfo->ver >= 9 && tiling == ISL_TILING_LINEAR ?
ISL_DIM_LAYOUT_GEN9_1D : ISL_DIM_LAYOUT_GEN4_2D); ISL_DIM_LAYOUT_GFX9_1D : ISL_DIM_LAYOUT_GFX4_2D);
case PIPE_TEXTURE_2D: case PIPE_TEXTURE_2D:
case PIPE_TEXTURE_2D_ARRAY: case PIPE_TEXTURE_2D_ARRAY:
case PIPE_TEXTURE_RECT: case PIPE_TEXTURE_RECT:
case PIPE_TEXTURE_CUBE: case PIPE_TEXTURE_CUBE:
case PIPE_TEXTURE_CUBE_ARRAY: case PIPE_TEXTURE_CUBE_ARRAY:
return ISL_DIM_LAYOUT_GEN4_2D; return ISL_DIM_LAYOUT_GFX4_2D;
case PIPE_TEXTURE_3D: case PIPE_TEXTURE_3D:
return (devinfo->ver >= 9 ? return (devinfo->ver >= 9 ?
ISL_DIM_LAYOUT_GEN4_2D : ISL_DIM_LAYOUT_GEN4_3D); ISL_DIM_LAYOUT_GFX4_2D : ISL_DIM_LAYOUT_GFX4_3D);
case PIPE_MAX_TEXTURE_TYPES: case PIPE_MAX_TEXTURE_TYPES:
case PIPE_BUFFER: case PIPE_BUFFER:
@ -628,7 +628,7 @@ iris_resource_configure_aux(struct iris_screen *screen,
assert(!res->mod_info || assert(!res->mod_info ||
res->mod_info->aux_usage == ISL_AUX_USAGE_NONE || res->mod_info->aux_usage == ISL_AUX_USAGE_NONE ||
res->mod_info->aux_usage == ISL_AUX_USAGE_CCS_E || res->mod_info->aux_usage == ISL_AUX_USAGE_CCS_E ||
res->mod_info->aux_usage == ISL_AUX_USAGE_GEN12_CCS_E || res->mod_info->aux_usage == ISL_AUX_USAGE_GFX12_CCS_E ||
res->mod_info->aux_usage == ISL_AUX_USAGE_MC); res->mod_info->aux_usage == ISL_AUX_USAGE_MC);
const bool has_mcs = !res->mod_info && const bool has_mcs = !res->mod_info &&
@ -679,7 +679,7 @@ iris_resource_configure_aux(struct iris_screen *screen,
} else if (has_ccs) { } else if (has_ccs) {
if (want_ccs_e_for_format(devinfo, res->surf.format)) { if (want_ccs_e_for_format(devinfo, res->surf.format)) {
res->aux.possible_usages |= devinfo->ver < 12 ? res->aux.possible_usages |= devinfo->ver < 12 ?
1 << ISL_AUX_USAGE_CCS_E : 1 << ISL_AUX_USAGE_GEN12_CCS_E; 1 << ISL_AUX_USAGE_CCS_E : 1 << ISL_AUX_USAGE_GFX12_CCS_E;
} else if (isl_format_supports_ccs_d(devinfo, res->surf.format)) { } else if (isl_format_supports_ccs_d(devinfo, res->surf.format)) {
res->aux.possible_usages |= 1 << ISL_AUX_USAGE_CCS_D; res->aux.possible_usages |= 1 << ISL_AUX_USAGE_CCS_D;
} }
@ -720,7 +720,7 @@ iris_resource_configure_aux(struct iris_screen *screen,
break; break;
case ISL_AUX_USAGE_CCS_D: case ISL_AUX_USAGE_CCS_D:
case ISL_AUX_USAGE_CCS_E: case ISL_AUX_USAGE_CCS_E:
case ISL_AUX_USAGE_GEN12_CCS_E: case ISL_AUX_USAGE_GFX12_CCS_E:
case ISL_AUX_USAGE_STC_CCS: case ISL_AUX_USAGE_STC_CCS:
case ISL_AUX_USAGE_MC: case ISL_AUX_USAGE_MC:
/* When CCS_E is used, we need to ensure that the CCS starts off in /* When CCS_E is used, we need to ensure that the CCS starts off in
@ -1951,7 +1951,7 @@ iris_transfer_map(struct pipe_context *ctx,
if (!map_would_stall && if (!map_would_stall &&
res->aux.usage != ISL_AUX_USAGE_CCS_E && res->aux.usage != ISL_AUX_USAGE_CCS_E &&
res->aux.usage != ISL_AUX_USAGE_GEN12_CCS_E) { res->aux.usage != ISL_AUX_USAGE_GFX12_CCS_E) {
no_gpu = true; no_gpu = true;
} }

6
src/intel/blorp/blorp.c
View file

@ -39,7 +39,7 @@ blorp_shader_type_to_name(enum blorp_shader_type type)
[BLORP_SHADER_TYPE_CLEAR] = "BLORP-clear", [BLORP_SHADER_TYPE_CLEAR] = "BLORP-clear",
[BLORP_SHADER_TYPE_MCS_PARTIAL_RESOLVE] = "BLORP-mcs-partial-resolve", [BLORP_SHADER_TYPE_MCS_PARTIAL_RESOLVE] = "BLORP-mcs-partial-resolve",
[BLORP_SHADER_TYPE_LAYER_OFFSET_VS] = "BLORP-layer-offset-vs", [BLORP_SHADER_TYPE_LAYER_OFFSET_VS] = "BLORP-layer-offset-vs",
[BLORP_SHADER_TYPE_GEN4_SF] = "BLORP-gfx4-sf", [BLORP_SHADER_TYPE_GFX4_SF] = "BLORP-gfx4-sf",
}; };
assert(type < ARRAY_SIZE(shader_name)); assert(type < ARRAY_SIZE(shader_name));
@ -267,7 +267,7 @@ blorp_compile_vs(struct blorp_context *blorp, void *mem_ctx,
} }
struct blorp_sf_key { struct blorp_sf_key {
enum blorp_shader_type shader_type; /* Must be BLORP_SHADER_TYPE_GEN4_SF */ enum blorp_shader_type shader_type; /* Must be BLORP_SHADER_TYPE_GFX4_SF */
struct brw_sf_prog_key key; struct brw_sf_prog_key key;
}; };
@ -285,7 +285,7 @@ blorp_ensure_sf_program(struct blorp_batch *batch,
return true; return true;
struct blorp_sf_key key = { struct blorp_sf_key key = {
.shader_type = BLORP_SHADER_TYPE_GEN4_SF, .shader_type = BLORP_SHADER_TYPE_GFX4_SF,
}; };
/* Everything gets compacted in vertex setup, so we just need a /* Everything gets compacted in vertex setup, so we just need a

8
src/intel/blorp/blorp_blit.c
View file

@ -2663,7 +2663,7 @@ blorp_copy(struct blorp_batch *batch,
params.src.aux_usage == ISL_AUX_USAGE_MCS || params.src.aux_usage == ISL_AUX_USAGE_MCS ||
params.src.aux_usage == ISL_AUX_USAGE_MCS_CCS || params.src.aux_usage == ISL_AUX_USAGE_MCS_CCS ||
params.src.aux_usage == ISL_AUX_USAGE_CCS_E || params.src.aux_usage == ISL_AUX_USAGE_CCS_E ||
params.src.aux_usage == ISL_AUX_USAGE_GEN12_CCS_E || params.src.aux_usage == ISL_AUX_USAGE_GFX12_CCS_E ||
params.src.aux_usage == ISL_AUX_USAGE_STC_CCS); params.src.aux_usage == ISL_AUX_USAGE_STC_CCS);
if (isl_aux_usage_has_hiz(params.src.aux_usage)) { if (isl_aux_usage_has_hiz(params.src.aux_usage)) {
@ -2680,10 +2680,10 @@ blorp_copy(struct blorp_batch *batch,
params.src.view.format = params.dst.surf.format; params.src.view.format = params.dst.surf.format;
params.dst.view.format = params.dst.surf.format; params.dst.view.format = params.dst.surf.format;
} else if (params.dst.aux_usage == ISL_AUX_USAGE_CCS_E || } else if (params.dst.aux_usage == ISL_AUX_USAGE_CCS_E ||
params.dst.aux_usage == ISL_AUX_USAGE_GEN12_CCS_E) { params.dst.aux_usage == ISL_AUX_USAGE_GFX12_CCS_E) {
params.dst.view.format = get_ccs_compatible_copy_format(dst_fmtl); params.dst.view.format = get_ccs_compatible_copy_format(dst_fmtl);
if (params.src.aux_usage == ISL_AUX_USAGE_CCS_E || if (params.src.aux_usage == ISL_AUX_USAGE_CCS_E ||
params.src.aux_usage == ISL_AUX_USAGE_GEN12_CCS_E) { params.src.aux_usage == ISL_AUX_USAGE_GFX12_CCS_E) {
params.src.view.format = get_ccs_compatible_copy_format(src_fmtl); params.src.view.format = get_ccs_compatible_copy_format(src_fmtl);
} else if (src_fmtl->bpb == dst_fmtl->bpb) { } else if (src_fmtl->bpb == dst_fmtl->bpb) {
params.src.view.format = params.dst.view.format; params.src.view.format = params.dst.view.format;
@ -2692,7 +2692,7 @@ blorp_copy(struct blorp_batch *batch,
get_copy_format_for_bpb(isl_dev, src_fmtl->bpb); get_copy_format_for_bpb(isl_dev, src_fmtl->bpb);
} }
} else if (params.src.aux_usage == ISL_AUX_USAGE_CCS_E || } else if (params.src.aux_usage == ISL_AUX_USAGE_CCS_E ||
params.src.aux_usage == ISL_AUX_USAGE_GEN12_CCS_E) { params.src.aux_usage == ISL_AUX_USAGE_GFX12_CCS_E) {
params.src.view.format = get_ccs_compatible_copy_format(src_fmtl); params.src.view.format = get_ccs_compatible_copy_format(src_fmtl);
if (src_fmtl->bpb == dst_fmtl->bpb) { if (src_fmtl->bpb == dst_fmtl->bpb) {
params.dst.view.format = params.src.view.format; params.dst.view.format = params.src.view.format;

6
src/intel/blorp/blorp_genX_exec.h
View file

@ -1413,7 +1413,7 @@ blorp_emit_surface_state(struct blorp_batch *batch,
struct isl_surf surf = surface->surf; struct isl_surf surf = surface->surf;
if (surf.dim == ISL_SURF_DIM_1D && if (surf.dim == ISL_SURF_DIM_1D &&
surf.dim_layout == ISL_DIM_LAYOUT_GEN4_2D) { surf.dim_layout == ISL_DIM_LAYOUT_GFX4_2D) {
assert(surf.logical_level0_px.height == 1); assert(surf.logical_level0_px.height == 1);
surf.dim = ISL_SURF_DIM_2D; surf.dim = ISL_SURF_DIM_2D;
} }
@ -1656,7 +1656,7 @@ blorp_emit_depth_stencil_config(struct blorp_batch *batch,
* However, we have a special layout that allows us to make it work * However, we have a special layout that allows us to make it work
* anyway by manually offsetting to the specified miplevel. * anyway by manually offsetting to the specified miplevel.
*/ */
assert(info.hiz_surf->dim_layout == ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ); assert(info.hiz_surf->dim_layout == ISL_DIM_LAYOUT_GFX6_STENCIL_HIZ);
uint32_t offset_B; uint32_t offset_B;
isl_surf_get_image_offset_B_tile_sa(info.hiz_surf, isl_surf_get_image_offset_B_tile_sa(info.hiz_surf,
info.view->base_level, 0, 0, info.view->base_level, 0, 0,
@ -1682,7 +1682,7 @@ blorp_emit_depth_stencil_config(struct blorp_batch *batch,
* However, we have a special layout that allows us to make it work * However, we have a special layout that allows us to make it work
* anyway by manually offsetting to the specified miplevel. * anyway by manually offsetting to the specified miplevel.
*/ */
assert(info.stencil_surf->dim_layout == ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ); assert(info.stencil_surf->dim_layout == ISL_DIM_LAYOUT_GFX6_STENCIL_HIZ);
uint32_t offset_B; uint32_t offset_B;
isl_surf_get_image_offset_B_tile_sa(info.stencil_surf, isl_surf_get_image_offset_B_tile_sa(info.stencil_surf,
info.view->base_level, 0, 0, info.view->base_level, 0, 0,

2
src/intel/blorp/blorp_priv.h
View file

@ -230,7 +230,7 @@ enum blorp_shader_type {
BLORP_SHADER_TYPE_CLEAR, BLORP_SHADER_TYPE_CLEAR,
BLORP_SHADER_TYPE_MCS_PARTIAL_RESOLVE, BLORP_SHADER_TYPE_MCS_PARTIAL_RESOLVE,
BLORP_SHADER_TYPE_LAYER_OFFSET_VS, BLORP_SHADER_TYPE_LAYER_OFFSET_VS,
BLORP_SHADER_TYPE_GEN4_SF, BLORP_SHADER_TYPE_GFX4_SF,
}; };
struct brw_blorp_blit_prog_key struct brw_blorp_blit_prog_key

4
src/intel/common/intel_aux_map.h
View file

@ -46,10 +46,10 @@ struct gen_device_info;
#define INTEL_AUX_MAP_ADDRESS_MASK 0x0000ffffffffff00ull #define INTEL_AUX_MAP_ADDRESS_MASK 0x0000ffffffffff00ull
#define INTEL_AUX_MAP_FORMAT_BITS_MASK 0xfff0000000000000ull #define INTEL_AUX_MAP_FORMAT_BITS_MASK 0xfff0000000000000ull
#define INTEL_AUX_MAP_ENTRY_VALID_BIT 0x1ull #define INTEL_AUX_MAP_ENTRY_VALID_BIT 0x1ull
#define INTEL_AUX_MAP_GEN12_CCS_SCALE 256 #define INTEL_AUX_MAP_GFX12_CCS_SCALE 256
#define INTEL_AUX_MAP_MAIN_PAGE_SIZE (64 * 1024) #define INTEL_AUX_MAP_MAIN_PAGE_SIZE (64 * 1024)
#define INTEL_AUX_MAP_AUX_PAGE_SIZE \ #define INTEL_AUX_MAP_AUX_PAGE_SIZE \
(INTEL_AUX_MAP_MAIN_PAGE_SIZE / INTEL_AUX_MAP_GEN12_CCS_SCALE) (INTEL_AUX_MAP_MAIN_PAGE_SIZE / INTEL_AUX_MAP_GFX12_CCS_SCALE)
struct intel_aux_map_context * struct intel_aux_map_context *
intel_aux_map_init(void *driver_ctx, intel_aux_map_init(void *driver_ctx,

2
src/intel/compiler/brw_compiler.h
View file

@ -577,7 +577,7 @@ struct brw_image_param {
/** /**
* Binding table index for the first gfx6 SOL binding. * Binding table index for the first gfx6 SOL binding.
*/ */
#define BRW_GEN6_SOL_BINDING_START 0 #define BRW_GFX6_SOL_BINDING_START 0
/** /**
* Stride in bytes between shader_time entries. * Stride in bytes between shader_time entries.

12
src/intel/compiler/brw_eu_defines.h
View file

@ -480,9 +480,9 @@ enum opcode {
*/ */
FS_OPCODE_SCHEDULING_FENCE, FS_OPCODE_SCHEDULING_FENCE,
SHADER_OPCODE_GEN4_SCRATCH_READ, SHADER_OPCODE_GFX4_SCRATCH_READ,
SHADER_OPCODE_GEN4_SCRATCH_WRITE, SHADER_OPCODE_GFX4_SCRATCH_WRITE,
SHADER_OPCODE_GEN7_SCRATCH_READ, SHADER_OPCODE_GFX7_SCRATCH_READ,
SHADER_OPCODE_SCRATCH_HEADER, SHADER_OPCODE_SCRATCH_HEADER,
@ -584,8 +584,8 @@ enum opcode {
FS_OPCODE_PIXEL_X, FS_OPCODE_PIXEL_X,
FS_OPCODE_PIXEL_Y, FS_OPCODE_PIXEL_Y,
FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD, FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD,
FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7, FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GFX7,
FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4, FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GFX4,
FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL, FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL,
FS_OPCODE_SET_SAMPLE_ID, FS_OPCODE_SET_SAMPLE_ID,
FS_OPCODE_PACK_HALF_2x16_SPLIT, FS_OPCODE_PACK_HALF_2x16_SPLIT,
@ -595,7 +595,7 @@ enum opcode {
VS_OPCODE_URB_WRITE, VS_OPCODE_URB_WRITE,
VS_OPCODE_PULL_CONSTANT_LOAD, VS_OPCODE_PULL_CONSTANT_LOAD,
VS_OPCODE_PULL_CONSTANT_LOAD_GEN7, VS_OPCODE_PULL_CONSTANT_LOAD_GFX7,
VS_OPCODE_UNPACK_FLAGS_SIMD4X2, VS_OPCODE_UNPACK_FLAGS_SIMD4X2,

18
src/intel/compiler/brw_fs.cpp
View file

@ -252,8 +252,8 @@ fs_inst::is_control_source(unsigned arg) const
{ {
switch (opcode) { switch (opcode) {
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD: case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7: case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GFX7:
case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4: case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GFX4:
return arg == 0; return arg == 0;
case SHADER_OPCODE_BROADCAST: case SHADER_OPCODE_BROADCAST:
@ -317,7 +317,7 @@ fs_inst::is_payload(unsigned arg) const
case SHADER_OPCODE_BARRIER: case SHADER_OPCODE_BARRIER:
return arg == 0; return arg == 0;
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7: case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GFX7:
return arg == 1; return arg == 1;
case SHADER_OPCODE_SEND: case SHADER_OPCODE_SEND:
@ -988,7 +988,7 @@ fs_inst::size_read(int arg) const
return 1; return 1;
break; break;
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7: case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GFX7:
/* The payload is actually stored in src1 */ /* The payload is actually stored in src1 */
if (arg == 1) if (arg == 1)
return mlen * REG_SIZE; return mlen * REG_SIZE;
@ -1174,11 +1174,11 @@ fs_inst::implied_mrf_writes() const
case FS_OPCODE_REP_FB_WRITE: case FS_OPCODE_REP_FB_WRITE:
return src[0].file == BAD_FILE ? 0 : 2; return src[0].file == BAD_FILE ? 0 : 2;
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD: case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
case SHADER_OPCODE_GEN4_SCRATCH_READ: case SHADER_OPCODE_GFX4_SCRATCH_READ:
return 1; return 1;
case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4: case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GFX4:
return mlen; return mlen;
case SHADER_OPCODE_GEN4_SCRATCH_WRITE: case SHADER_OPCODE_GFX4_SCRATCH_WRITE:
return mlen; return mlen;
default: default:
unreachable("not reached"); unreachable("not reached");
@ -3799,7 +3799,7 @@ fs_visitor::lower_uniform_pull_constant_loads()
ubld.group(1, 0).MOV(component(payload, 2), ubld.group(1, 0).MOV(component(payload, 2),
brw_imm_ud(inst->src[1].ud / 16)); brw_imm_ud(inst->src[1].ud / 16));
inst->opcode = FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7; inst->opcode = FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GFX7;
inst->src[1] = payload; inst->src[1] = payload;
inst->header_size = 1; inst->header_size = 1;
inst->mlen = 1; inst->mlen = 1;
@ -6103,7 +6103,7 @@ lower_varying_pull_constant_logical_send(const fs_builder &bld, fs_inst *inst)
bld.MOV(byte_offset(payload, REG_SIZE), inst->src[1]); bld.MOV(byte_offset(payload, REG_SIZE), inst->src[1]);
inst->opcode = FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4; inst->opcode = FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GFX4;
inst->resize_sources(1); inst->resize_sources(1);
inst->base_mrf = payload.nr; inst->base_mrf = payload.nr;
inst->header_size = 1; inst->header_size = 1;

2
src/intel/compiler/brw_fs_copy_propagation.cpp
View file

@ -523,7 +523,7 @@ fs_visitor::try_copy_propagate(fs_inst *inst, int arg, acp_entry *entry)
} }
if (has_source_modifiers && if (has_source_modifiers &&
inst->opcode == SHADER_OPCODE_GEN4_SCRATCH_WRITE) inst->opcode == SHADER_OPCODE_GFX4_SCRATCH_WRITE)
return false; return false;
/* Some instructions implemented in the generator backend, such as /* Some instructions implemented in the generator backend, such as

10
src/intel/compiler/brw_fs_generator.cpp
View file

@ -2331,17 +2331,17 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
generate_ddy(inst, dst, src[0]); generate_ddy(inst, dst, src[0]);
break; break;
case SHADER_OPCODE_GEN4_SCRATCH_WRITE: case SHADER_OPCODE_GFX4_SCRATCH_WRITE:
generate_scratch_write(inst, src[0]); generate_scratch_write(inst, src[0]);
spill_count++; spill_count++;
break; break;
case SHADER_OPCODE_GEN4_SCRATCH_READ: case SHADER_OPCODE_GFX4_SCRATCH_READ:
generate_scratch_read(inst, dst); generate_scratch_read(inst, dst);
fill_count++; fill_count++;
break; break;
case SHADER_OPCODE_GEN7_SCRATCH_READ: case SHADER_OPCODE_GFX7_SCRATCH_READ:
generate_scratch_read_gfx7(inst, dst); generate_scratch_read_gfx7(inst, dst);
fill_count++; fill_count++;
break; break;
@ -2379,13 +2379,13 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
send_count++; send_count++;
break; break;
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7: case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GFX7:
assert(inst->force_writemask_all); assert(inst->force_writemask_all);
generate_uniform_pull_constant_load_gfx7(inst, dst, src[0], src[1]); generate_uniform_pull_constant_load_gfx7(inst, dst, src[0], src[1]);
send_count++; send_count++;
break; break;
case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4: case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GFX4:
generate_varying_pull_constant_load_gfx4(inst, dst, src[0]); generate_varying_pull_constant_load_gfx4(inst, dst, src[0]);
send_count++; send_count++;
break; break;

10
src/intel/compiler/brw_fs_reg_allocate.cpp
View file

@ -704,8 +704,8 @@ fs_reg_alloc::setup_inst_interference(const fs_inst *inst)
* message as source. So as we will have an overlap for sure, we create * message as source. So as we will have an overlap for sure, we create
* an interference between destination and grf127. * an interference between destination and grf127.
*/ */
if ((inst->opcode == SHADER_OPCODE_GEN7_SCRATCH_READ || if ((inst->opcode == SHADER_OPCODE_GFX7_SCRATCH_READ ||
inst->opcode == SHADER_OPCODE_GEN4_SCRATCH_READ) && inst->opcode == SHADER_OPCODE_GFX4_SCRATCH_READ) &&
inst->dst.file == VGRF) inst->dst.file == VGRF)
ra_add_node_interference(g, first_vgrf_node + inst->dst.nr, ra_add_node_interference(g, first_vgrf_node + inst->dst.nr,
grf127_send_hack_node); grf127_send_hack_node);
@ -921,10 +921,10 @@ fs_reg_alloc::emit_unspill(const fs_builder &bld, fs_reg dst,
* the address as part of the message header, so we're better off * the address as part of the message header, so we're better off
* using plain old oword block reads. * using plain old oword block reads.
*/ */
unspill_inst = bld.emit(SHADER_OPCODE_GEN7_SCRATCH_READ, dst); unspill_inst = bld.emit(SHADER_OPCODE_GFX7_SCRATCH_READ, dst);
unspill_inst->offset = spill_offset; unspill_inst->offset = spill_offset;
} else { } else {
unspill_inst = bld.emit(SHADER_OPCODE_GEN4_SCRATCH_READ, dst); unspill_inst = bld.emit(SHADER_OPCODE_GFX4_SCRATCH_READ, dst);
unspill_inst->offset = spill_offset; unspill_inst->offset = spill_offset;
unspill_inst->base_mrf = spill_base_mrf(bld.shader); unspill_inst->base_mrf = spill_base_mrf(bld.shader);
unspill_inst->mlen = 1; /* header contains offset */ unspill_inst->mlen = 1; /* header contains offset */
@ -972,7 +972,7 @@ fs_reg_alloc::emit_spill(const fs_builder &bld, fs_reg src,
0 /* not a render target */, 0 /* not a render target */,
false /* send_commit_msg */); false /* send_commit_msg */);
} else { } else {
spill_inst = bld.emit(SHADER_OPCODE_GEN4_SCRATCH_WRITE, spill_inst = bld.emit(SHADER_OPCODE_GFX4_SCRATCH_WRITE,
bld.null_reg_f(), src); bld.null_reg_f(), src);
spill_inst->offset = spill_offset; spill_inst->offset = spill_offset;
spill_inst->mlen = 1 + reg_size; /* header, value */ spill_inst->mlen = 1 + reg_size; /* header, value */

12
src/intel/compiler/brw_ir_performance.cpp
View file

@ -903,7 +903,7 @@ namespace {
case SHADER_OPCODE_TG4: case SHADER_OPCODE_TG4:
case SHADER_OPCODE_TG4_OFFSET: case SHADER_OPCODE_TG4_OFFSET:
case SHADER_OPCODE_SAMPLEINFO: case SHADER_OPCODE_SAMPLEINFO:
case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4: case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GFX4:
return calculate_desc(info, unit_sampler, 2, 0, 0, 0, 16 /* XXX */, return calculate_desc(info, unit_sampler, 2, 0, 0, 0, 16 /* XXX */,
8 /* XXX */, 750 /* XXX */, 0, 0, 8 /* XXX */, 750 /* XXX */, 0, 0,
2 /* XXX */, 0); 2 /* XXX */, 0);
@ -948,9 +948,9 @@ namespace {
abort(); abort();
} }
case SHADER_OPCODE_GEN4_SCRATCH_READ: case SHADER_OPCODE_GFX4_SCRATCH_READ:
case SHADER_OPCODE_GEN4_SCRATCH_WRITE: case SHADER_OPCODE_GFX4_SCRATCH_WRITE:
case SHADER_OPCODE_GEN7_SCRATCH_READ: case SHADER_OPCODE_GFX7_SCRATCH_READ:
return calculate_desc(info, unit_dp_dc, 2, 0, 0, 0, 8 /* XXX */, return calculate_desc(info, unit_dp_dc, 2, 0, 0, 0, 8 /* XXX */,
10 /* XXX */, 100 /* XXX */, 0, 0, 0, 0); 10 /* XXX */, 100 /* XXX */, 0, 0, 0, 0);
@ -989,12 +989,12 @@ namespace {
abort(); abort();
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD: case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7: case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GFX7:
return calculate_desc(info, unit_dp_cc, 2, 0, 0, 0, 16 /* XXX */, return calculate_desc(info, unit_dp_cc, 2, 0, 0, 0, 16 /* XXX */,
10 /* XXX */, 100 /* XXX */, 0, 0, 0, 0); 10 /* XXX */, 100 /* XXX */, 0, 0, 0, 0);
case VS_OPCODE_PULL_CONSTANT_LOAD: case VS_OPCODE_PULL_CONSTANT_LOAD:
case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7: case VS_OPCODE_PULL_CONSTANT_LOAD_GFX7:
return calculate_desc(info, unit_sampler, 2, 0, 0, 0, 16, return calculate_desc(info, unit_sampler, 2, 0, 0, 0, 16,
8, 750, 0, 0, 2, 0); 8, 750, 0, 0, 2, 0);

4
src/intel/compiler/brw_ir_vec4.h
View file

@ -354,8 +354,8 @@ public:
case VS_OPCODE_PULL_CONSTANT_LOAD: case VS_OPCODE_PULL_CONSTANT_LOAD:
case GS_OPCODE_SET_PRIMITIVE_ID: case GS_OPCODE_SET_PRIMITIVE_ID:
case GS_OPCODE_GET_INSTANCE_ID: case GS_OPCODE_GET_INSTANCE_ID:
case SHADER_OPCODE_GEN4_SCRATCH_READ: case SHADER_OPCODE_GFX4_SCRATCH_READ:
case SHADER_OPCODE_GEN4_SCRATCH_WRITE: case SHADER_OPCODE_GFX4_SCRATCH_WRITE:
return true; return true;
default: default:
return false; return false;

6
src/intel/compiler/brw_schedule_instructions.cpp
View file

@ -322,9 +322,9 @@ schedule_node::set_latency_gfx7(bool is_haswell)
latency = 100; latency = 100;
break; break;
case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4: case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GFX4:
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD: case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7: case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GFX7:
case VS_OPCODE_PULL_CONSTANT_LOAD: case VS_OPCODE_PULL_CONSTANT_LOAD:
/* testing using varying-index pull constants: /* testing using varying-index pull constants:
* *
@ -355,7 +355,7 @@ schedule_node::set_latency_gfx7(bool is_haswell)
latency = 200; latency = 200;
break; break;
case SHADER_OPCODE_GEN7_SCRATCH_READ: case SHADER_OPCODE_GFX7_SCRATCH_READ:
/* Testing a load from offset 0, that had been previously written: /* Testing a load from offset 0, that had been previously written:
* *
* send(8) g114<1>UW g0<8,8,1>F data (0, 0, 0) mlen 1 rlen 1 { align1 WE_normal 1Q }; * send(8) g114<1>UW g0<8,8,1>F data (0, 0, 0) mlen 1 rlen 1 { align1 WE_normal 1Q };

14
src/intel/compiler/brw_shader.cpp
View file

@ -359,11 +359,11 @@ brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op)
case FS_OPCODE_PACK: case FS_OPCODE_PACK:
return "pack"; return "pack";
case SHADER_OPCODE_GEN4_SCRATCH_READ: case SHADER_OPCODE_GFX4_SCRATCH_READ:
return "gfx4_scratch_read"; return "gfx4_scratch_read";
case SHADER_OPCODE_GEN4_SCRATCH_WRITE: case SHADER_OPCODE_GFX4_SCRATCH_WRITE:
return "gfx4_scratch_write"; return "gfx4_scratch_write";
case SHADER_OPCODE_GEN7_SCRATCH_READ: case SHADER_OPCODE_GFX7_SCRATCH_READ:
return "gfx7_scratch_read"; return "gfx7_scratch_read";
case SHADER_OPCODE_SCRATCH_HEADER: case SHADER_OPCODE_SCRATCH_HEADER:
return "scratch_header"; return "scratch_header";
@ -441,9 +441,9 @@ brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op)
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD: case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
return "uniform_pull_const"; return "uniform_pull_const";
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7: case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GFX7:
return "uniform_pull_const_gfx7"; return "uniform_pull_const_gfx7";
case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4: case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GFX4:
return "varying_pull_const_gfx4"; return "varying_pull_const_gfx4";
case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL: case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL:
return "varying_pull_const_logical"; return "varying_pull_const_logical";
@ -468,7 +468,7 @@ brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op)
return "vs_urb_write"; return "vs_urb_write";
case VS_OPCODE_PULL_CONSTANT_LOAD: case VS_OPCODE_PULL_CONSTANT_LOAD:
return "pull_constant_load"; return "pull_constant_load";
case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7: case VS_OPCODE_PULL_CONSTANT_LOAD_GFX7:
return "pull_constant_load_gfx7"; return "pull_constant_load_gfx7";
case VS_OPCODE_UNPACK_FLAGS_SIMD4X2: case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
@ -1100,7 +1100,7 @@ backend_instruction::has_side_effects() const
case VEC4_OPCODE_UNTYPED_ATOMIC: case VEC4_OPCODE_UNTYPED_ATOMIC:
case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL: case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL: case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL:
case SHADER_OPCODE_GEN4_SCRATCH_WRITE: case SHADER_OPCODE_GFX4_SCRATCH_WRITE:
case VEC4_OPCODE_UNTYPED_SURFACE_WRITE: case VEC4_OPCODE_UNTYPED_SURFACE_WRITE:
case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL: case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL: case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL:

16
src/intel/compiler/brw_vec4.cpp
View file

@ -151,7 +151,7 @@ vec4_instruction::is_send_from_grf() const
{ {
switch (opcode) { switch (opcode) {
case SHADER_OPCODE_SHADER_TIME_ADD: case SHADER_OPCODE_SHADER_TIME_ADD:
case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7: case VS_OPCODE_PULL_CONSTANT_LOAD_GFX7:
case VEC4_OPCODE_UNTYPED_ATOMIC: case VEC4_OPCODE_UNTYPED_ATOMIC:
case VEC4_OPCODE_UNTYPED_SURFACE_READ: case VEC4_OPCODE_UNTYPED_SURFACE_READ:
case VEC4_OPCODE_UNTYPED_SURFACE_WRITE: case VEC4_OPCODE_UNTYPED_SURFACE_WRITE:
@ -215,7 +215,7 @@ vec4_instruction::size_read(unsigned arg) const
if (arg == 0) if (arg == 0)
return mlen * REG_SIZE; return mlen * REG_SIZE;
break; break;
case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7: case VS_OPCODE_PULL_CONSTANT_LOAD_GFX7:
if (arg == 1) if (arg == 1)
return mlen * REG_SIZE; return mlen * REG_SIZE;
break; break;
@ -274,7 +274,7 @@ bool
vec4_instruction::can_do_writemask(const struct gen_device_info *devinfo) vec4_instruction::can_do_writemask(const struct gen_device_info *devinfo)
{ {
switch (opcode) { switch (opcode) {
case SHADER_OPCODE_GEN4_SCRATCH_READ: case SHADER_OPCODE_GFX4_SCRATCH_READ:
case VEC4_OPCODE_DOUBLE_TO_F32: case VEC4_OPCODE_DOUBLE_TO_F32:
case VEC4_OPCODE_DOUBLE_TO_D32: case VEC4_OPCODE_DOUBLE_TO_D32:
case VEC4_OPCODE_DOUBLE_TO_U32: case VEC4_OPCODE_DOUBLE_TO_U32:
@ -284,7 +284,7 @@ vec4_instruction::can_do_writemask(const struct gen_device_info *devinfo)
case VEC4_OPCODE_SET_LOW_32BIT: case VEC4_OPCODE_SET_LOW_32BIT:
case VEC4_OPCODE_SET_HIGH_32BIT: case VEC4_OPCODE_SET_HIGH_32BIT:
case VS_OPCODE_PULL_CONSTANT_LOAD: case VS_OPCODE_PULL_CONSTANT_LOAD:
case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7: case VS_OPCODE_PULL_CONSTANT_LOAD_GFX7:
case TCS_OPCODE_SET_INPUT_URB_OFFSETS: case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS: case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
case TES_OPCODE_CREATE_INPUT_READ_HEADER: case TES_OPCODE_CREATE_INPUT_READ_HEADER:
@ -349,9 +349,9 @@ vec4_instruction::implied_mrf_writes() const
return 1; return 1;
case VS_OPCODE_PULL_CONSTANT_LOAD: case VS_OPCODE_PULL_CONSTANT_LOAD:
return 2; return 2;
case SHADER_OPCODE_GEN4_SCRATCH_READ: case SHADER_OPCODE_GFX4_SCRATCH_READ:
return 2; return 2;
case SHADER_OPCODE_GEN4_SCRATCH_WRITE: case SHADER_OPCODE_GFX4_SCRATCH_WRITE:
return 3; return 3;
case GS_OPCODE_URB_WRITE: case GS_OPCODE_URB_WRITE:
case GS_OPCODE_URB_WRITE_ALLOCATE: case GS_OPCODE_URB_WRITE_ALLOCATE:
@ -2179,8 +2179,8 @@ get_lowered_simd_width(const struct gen_device_info *devinfo,
{ {
/* Do not split some instructions that require special handling */ /* Do not split some instructions that require special handling */
switch (inst->opcode) { switch (inst->opcode) {
case SHADER_OPCODE_GEN4_SCRATCH_READ: case SHADER_OPCODE_GFX4_SCRATCH_READ:
case SHADER_OPCODE_GEN4_SCRATCH_WRITE: case SHADER_OPCODE_GFX4_SCRATCH_WRITE:
return inst->exec_size; return inst->exec_size;
default: default:
break; break;

2
src/intel/compiler/brw_vec4_copy_propagation.cpp
View file

@ -366,7 +366,7 @@ try_copy_propagate(const struct gen_device_info *devinfo,
return false; return false;
if (has_source_modifiers && if (has_source_modifiers &&
(inst->opcode == SHADER_OPCODE_GEN4_SCRATCH_WRITE || (inst->opcode == SHADER_OPCODE_GFX4_SCRATCH_WRITE ||
inst->opcode == VEC4_OPCODE_PICK_HIGH_32BIT)) inst->opcode == VEC4_OPCODE_PICK_HIGH_32BIT))
return false; return false;

8
src/intel/compiler/brw_vec4_generator.cpp
View file

@ -506,7 +506,7 @@ generate_gs_svb_write(struct brw_codegen *p,
final_write ? src1 : brw_null_reg(), /* dest == src1 */ final_write ? src1 : brw_null_reg(), /* dest == src1 */
1, /* msg_reg_nr */ 1, /* msg_reg_nr */
dst, /* src0 == previous dst */ dst, /* src0 == previous dst */
BRW_GEN6_SOL_BINDING_START + binding, /* binding_table_index */ BRW_GFX6_SOL_BINDING_START + binding, /* binding_table_index */
final_write); /* send_commit_msg */ final_write); /* send_commit_msg */
/* Finally, wait for the write commit to occur so that we can proceed to /* Finally, wait for the write commit to occur so that we can proceed to
@ -1774,12 +1774,12 @@ generate_code(struct brw_codegen *p,
send_count++; send_count++;
break; break;
case SHADER_OPCODE_GEN4_SCRATCH_READ: case SHADER_OPCODE_GFX4_SCRATCH_READ:
generate_scratch_read(p, inst, dst, src[0]); generate_scratch_read(p, inst, dst, src[0]);
fill_count++; fill_count++;
break; break;
case SHADER_OPCODE_GEN4_SCRATCH_WRITE: case SHADER_OPCODE_GFX4_SCRATCH_WRITE:
generate_scratch_write(p, inst, dst, src[0], src[1]); generate_scratch_write(p, inst, dst, src[0], src[1]);
spill_count++; spill_count++;
break; break;
@ -1789,7 +1789,7 @@ generate_code(struct brw_codegen *p,
send_count++; send_count++;
break; break;
case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7: case VS_OPCODE_PULL_CONSTANT_LOAD_GFX7:
generate_pull_constant_load_gfx7(p, inst, dst, src[0], src[1]); generate_pull_constant_load_gfx7(p, inst, dst, src[0], src[1]);
send_count++; send_count++;
break; break;

8
src/intel/compiler/brw_vec4_reg_allocate.cpp
View file

@ -330,8 +330,8 @@ can_use_scratch_for_source(const vec4_instruction *inst, unsigned i,
* other registers (that won't read/write scratch_reg) do not stop us from * other registers (that won't read/write scratch_reg) do not stop us from
* reusing scratch_reg for this instruction. * reusing scratch_reg for this instruction.
*/ */
if (prev_inst->opcode == SHADER_OPCODE_GEN4_SCRATCH_WRITE || if (prev_inst->opcode == SHADER_OPCODE_GFX4_SCRATCH_WRITE ||
prev_inst->opcode == SHADER_OPCODE_GEN4_SCRATCH_READ) prev_inst->opcode == SHADER_OPCODE_GFX4_SCRATCH_READ)
continue; continue;
/* If the previous instruction does not write to scratch_reg, then check /* If the previous instruction does not write to scratch_reg, then check
@ -466,8 +466,8 @@ vec4_visitor::evaluate_spill_costs(float *spill_costs, bool *no_spill)
loop_scale /= 10; loop_scale /= 10;
break; break;
case SHADER_OPCODE_GEN4_SCRATCH_READ: case SHADER_OPCODE_GFX4_SCRATCH_READ:
case SHADER_OPCODE_GEN4_SCRATCH_WRITE: case SHADER_OPCODE_GFX4_SCRATCH_WRITE:
for (int i = 0; i < 3; i++) { for (int i = 0; i < 3; i++) {
if (inst->src[i].file == VGRF) if (inst->src[i].file == VGRF)
no_spill[inst->src[i].nr] = true; no_spill[inst->src[i].nr] = true;

6
src/intel/compiler/brw_vec4_visitor.cpp
View file

@ -257,7 +257,7 @@ vec4_visitor::SCRATCH_READ(const dst_reg &dst, const src_reg &index)
{ {
vec4_instruction *inst; vec4_instruction *inst;
inst = new(mem_ctx) vec4_instruction(SHADER_OPCODE_GEN4_SCRATCH_READ, inst = new(mem_ctx) vec4_instruction(SHADER_OPCODE_GFX4_SCRATCH_READ,
dst, index); dst, index);
inst->base_mrf = FIRST_SPILL_MRF(devinfo->ver) + 1; inst->base_mrf = FIRST_SPILL_MRF(devinfo->ver) + 1;
inst->mlen = 2; inst->mlen = 2;
@ -271,7 +271,7 @@ vec4_visitor::SCRATCH_WRITE(const dst_reg &dst, const src_reg &src,
{ {
vec4_instruction *inst; vec4_instruction *inst;
inst = new(mem_ctx) vec4_instruction(SHADER_OPCODE_GEN4_SCRATCH_WRITE, inst = new(mem_ctx) vec4_instruction(SHADER_OPCODE_GFX4_SCRATCH_WRITE,
dst, src, index); dst, src, index);
inst->base_mrf = FIRST_SPILL_MRF(devinfo->ver); inst->base_mrf = FIRST_SPILL_MRF(devinfo->ver);
inst->mlen = 3; inst->mlen = 3;
@ -752,7 +752,7 @@ vec4_visitor::emit_pull_constant_load_reg(dst_reg dst,
else else
emit(pull); emit(pull);
pull = new(mem_ctx) vec4_instruction(VS_OPCODE_PULL_CONSTANT_LOAD_GEN7, pull = new(mem_ctx) vec4_instruction(VS_OPCODE_PULL_CONSTANT_LOAD_GFX7,
dst, dst,
surf_index, surf_index,
src_reg(grf_offset)); src_reg(grf_offset));

2
src/intel/genxml/gen125.xml
View file

@ -1,5 +1,5 @@
<?xml version="1.0" ?> <?xml version="1.0" ?>
<genxml name="GEN125" gen="12.5"> <genxml name="GFX125" gen="12.5">
<enum name="3D_Color_Buffer_Blend_Factor" prefix="BLENDFACTOR"> <enum name="3D_Color_Buffer_Blend_Factor" prefix="BLENDFACTOR">
<value name="ONE" value="1"/> <value name="ONE" value="1"/>

2
src/intel/isl/README
View file

@ -71,7 +71,7 @@ Definitions
For example, the logical array length of a 3D surface is always 1, even on For example, the logical array length of a 3D surface is always 1, even on
Gfx9 where the surface's memory layout is that of an array surface Gfx9 where the surface's memory layout is that of an array surface
(ISL_DIM_LAYOUT_GEN4_2D). (ISL_DIM_LAYOUT_GFX4_2D).
- Physical Surface Samples (sa): - Physical Surface Samples (sa):

118
src/intel/isl/isl.c
View file

@ -410,7 +410,7 @@ isl_tiling_get_info(enum isl_tiling tiling,
phys_B = isl_extent2d(128, 32); phys_B = isl_extent2d(128, 32);
break; break;
case ISL_TILING_GEN12_CCS: case ISL_TILING_GFX12_CCS:
/* From the Bspec, Gen Graphics > Gfx12 > Memory Data Formats > Memory /* From the Bspec, Gen Graphics > Gfx12 > Memory Data Formats > Memory
* Compression > Memory Compression - Gfx12: * Compression > Memory Compression - Gfx12:
* *
@ -516,7 +516,7 @@ isl_surf_choose_tiling(const struct isl_device *dev,
UNUSED bool ivb_ccs = ISL_GFX_VER(dev) < 12 && UNUSED bool ivb_ccs = ISL_GFX_VER(dev) < 12 &&
tiling_flags == ISL_TILING_CCS_BIT; tiling_flags == ISL_TILING_CCS_BIT;
UNUSED bool tgl_ccs = ISL_GFX_VER(dev) >= 12 && UNUSED bool tgl_ccs = ISL_GFX_VER(dev) >= 12 &&
tiling_flags == ISL_TILING_GEN12_CCS_BIT; tiling_flags == ISL_TILING_GFX12_CCS_BIT;
assert(ivb_ccs != tgl_ccs); assert(ivb_ccs != tgl_ccs);
*tiling = isl_tiling_flag_to_enum(tiling_flags); *tiling = isl_tiling_flag_to_enum(tiling_flags);
return true; return true;
@ -618,8 +618,8 @@ isl_choose_array_pitch_span(const struct isl_device *dev,
const struct isl_extent4d *phys_level0_sa) const struct isl_extent4d *phys_level0_sa)
{ {
switch (dim_layout) { switch (dim_layout) {
case ISL_DIM_LAYOUT_GEN9_1D: case ISL_DIM_LAYOUT_GFX9_1D:
case ISL_DIM_LAYOUT_GEN4_2D: case ISL_DIM_LAYOUT_GFX4_2D:
if (ISL_GFX_VER(dev) >= 8) { if (ISL_GFX_VER(dev) >= 8) {
/* QPitch becomes programmable in Broadwell. So choose the /* QPitch becomes programmable in Broadwell. So choose the
* most compact QPitch possible in order to conserve memory. * most compact QPitch possible in order to conserve memory.
@ -710,13 +710,13 @@ isl_choose_array_pitch_span(const struct isl_device *dev,
return ISL_ARRAY_PITCH_SPAN_FULL; return ISL_ARRAY_PITCH_SPAN_FULL;
} }
case ISL_DIM_LAYOUT_GEN4_3D: case ISL_DIM_LAYOUT_GFX4_3D:
/* The hardware will never use the QPitch. So choose the most /* The hardware will never use the QPitch. So choose the most
* compact QPitch possible in order to conserve memory. * compact QPitch possible in order to conserve memory.
*/ */
return ISL_ARRAY_PITCH_SPAN_COMPACT; return ISL_ARRAY_PITCH_SPAN_COMPACT;
case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ: case ISL_DIM_LAYOUT_GFX6_STENCIL_HIZ:
/* Each array image in the gfx6 stencil of HiZ surface is compact in the /* Each array image in the gfx6 stencil of HiZ surface is compact in the
* sense that every LOD is a compact array of the same size as LOD0. * sense that every LOD is a compact array of the same size as LOD0.
*/ */
@ -800,7 +800,7 @@ isl_surf_choose_dim_layout(const struct isl_device *dev,
/* Sandy bridge needs a special layout for HiZ and stencil. */ /* Sandy bridge needs a special layout for HiZ and stencil. */
if (ISL_GFX_VER(dev) == 6 && if (ISL_GFX_VER(dev) == 6 &&
(tiling == ISL_TILING_W || tiling == ISL_TILING_HIZ)) (tiling == ISL_TILING_W || tiling == ISL_TILING_HIZ))
return ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ; return ISL_DIM_LAYOUT_GFX6_STENCIL_HIZ;
if (ISL_GFX_VER(dev) >= 9) { if (ISL_GFX_VER(dev) >= 9) {
switch (logical_dim) { switch (logical_dim) {
@ -816,16 +816,16 @@ isl_surf_choose_dim_layout(const struct isl_device *dev,
* can be defined as a 2D tiled surface (e.g. TileY or TileX) with * can be defined as a 2D tiled surface (e.g. TileY or TileX) with
* a height of 0. * a height of 0.
* *
* In other words, ISL_DIM_LAYOUT_GEN9_1D is only used for linear * In other words, ISL_DIM_LAYOUT_GFX9_1D is only used for linear
* surfaces and, for tiled surfaces, ISL_DIM_LAYOUT_GEN4_2D is used. * surfaces and, for tiled surfaces, ISL_DIM_LAYOUT_GFX4_2D is used.
*/ */
if (tiling == ISL_TILING_LINEAR) if (tiling == ISL_TILING_LINEAR)
return ISL_DIM_LAYOUT_GEN9_1D; return ISL_DIM_LAYOUT_GFX9_1D;
else else
return ISL_DIM_LAYOUT_GEN4_2D; return ISL_DIM_LAYOUT_GFX4_2D;
case ISL_SURF_DIM_2D: case ISL_SURF_DIM_2D:
case ISL_SURF_DIM_3D: case ISL_SURF_DIM_3D:
return ISL_DIM_LAYOUT_GEN4_2D; return ISL_DIM_LAYOUT_GFX4_2D;
} }
} else { } else {
switch (logical_dim) { switch (logical_dim) {
@ -839,16 +839,16 @@ isl_surf_choose_dim_layout(const struct isl_device *dev,
* is not reduced for each MIP. * is not reduced for each MIP.
*/ */
if (ISL_GFX_VER(dev) == 4 && (usage & ISL_SURF_USAGE_CUBE_BIT)) if (ISL_GFX_VER(dev) == 4 && (usage & ISL_SURF_USAGE_CUBE_BIT))
return ISL_DIM_LAYOUT_GEN4_3D; return ISL_DIM_LAYOUT_GFX4_3D;
return ISL_DIM_LAYOUT_GEN4_2D; return ISL_DIM_LAYOUT_GFX4_2D;
case ISL_SURF_DIM_3D: case ISL_SURF_DIM_3D:
return ISL_DIM_LAYOUT_GEN4_3D; return ISL_DIM_LAYOUT_GFX4_3D;
} }
} }
unreachable("bad isl_surf_dim"); unreachable("bad isl_surf_dim");
return ISL_DIM_LAYOUT_GEN4_2D; return ISL_DIM_LAYOUT_GFX4_2D;
} }
/** /**
@ -875,12 +875,12 @@ isl_calc_phys_level0_extent_sa(const struct isl_device *dev,
assert(info->samples == 1); assert(info->samples == 1);
switch (dim_layout) { switch (dim_layout) {
case ISL_DIM_LAYOUT_GEN4_3D: case ISL_DIM_LAYOUT_GFX4_3D:
unreachable("bad isl_dim_layout"); unreachable("bad isl_dim_layout");
case ISL_DIM_LAYOUT_GEN9_1D: case ISL_DIM_LAYOUT_GFX9_1D:
case ISL_DIM_LAYOUT_GEN4_2D: case ISL_DIM_LAYOUT_GFX4_2D:
case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ: case ISL_DIM_LAYOUT_GFX6_STENCIL_HIZ:
*phys_level0_sa = (struct isl_extent4d) { *phys_level0_sa = (struct isl_extent4d) {
.w = info->width, .w = info->width,
.h = 1, .h = 1,
@ -893,10 +893,10 @@ isl_calc_phys_level0_extent_sa(const struct isl_device *dev,
case ISL_SURF_DIM_2D: case ISL_SURF_DIM_2D:
if (ISL_GFX_VER(dev) == 4 && (info->usage & ISL_SURF_USAGE_CUBE_BIT)) if (ISL_GFX_VER(dev) == 4 && (info->usage & ISL_SURF_USAGE_CUBE_BIT))
assert(dim_layout == ISL_DIM_LAYOUT_GEN4_3D); assert(dim_layout == ISL_DIM_LAYOUT_GFX4_3D);
else else
assert(dim_layout == ISL_DIM_LAYOUT_GEN4_2D || assert(dim_layout == ISL_DIM_LAYOUT_GFX4_2D ||
dim_layout == ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ); dim_layout == ISL_DIM_LAYOUT_GFX6_STENCIL_HIZ);
if (tiling == ISL_TILING_Ys && info->samples > 1) if (tiling == ISL_TILING_Ys && info->samples > 1)
isl_finishme("%s:%s: multisample TileYs layout", __FILE__, __func__); isl_finishme("%s:%s: multisample TileYs layout", __FILE__, __func__);
@ -957,11 +957,11 @@ isl_calc_phys_level0_extent_sa(const struct isl_device *dev,
} }
switch (dim_layout) { switch (dim_layout) {
case ISL_DIM_LAYOUT_GEN9_1D: case ISL_DIM_LAYOUT_GFX9_1D:
case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ: case ISL_DIM_LAYOUT_GFX6_STENCIL_HIZ:
unreachable("bad isl_dim_layout"); unreachable("bad isl_dim_layout");
case ISL_DIM_LAYOUT_GEN4_2D: case ISL_DIM_LAYOUT_GFX4_2D:
assert(ISL_GFX_VER(dev) >= 9); assert(ISL_GFX_VER(dev) >= 9);
*phys_level0_sa = (struct isl_extent4d) { *phys_level0_sa = (struct isl_extent4d) {
@ -972,7 +972,7 @@ isl_calc_phys_level0_extent_sa(const struct isl_device *dev,
}; };
break; break;
case ISL_DIM_LAYOUT_GEN4_3D: case ISL_DIM_LAYOUT_GFX4_3D:
assert(ISL_GFX_VER(dev) < 9); assert(ISL_GFX_VER(dev) < 9);
*phys_level0_sa = (struct isl_extent4d) { *phys_level0_sa = (struct isl_extent4d) {
.w = info->width, .w = info->width,
@ -1093,7 +1093,7 @@ isl_calc_array_pitch_el_rows_gfx4_2d(
/** /**
* A variant of isl_calc_phys_slice0_extent_sa() specific to * A variant of isl_calc_phys_slice0_extent_sa() specific to
* ISL_DIM_LAYOUT_GEN4_2D. * ISL_DIM_LAYOUT_GFX4_2D.
*/ */
static void static void
isl_calc_phys_slice0_extent_sa_gfx4_2d( isl_calc_phys_slice0_extent_sa_gfx4_2d(
@ -1196,7 +1196,7 @@ isl_calc_phys_total_extent_el_gfx4_2d(
/** /**
* A variant of isl_calc_phys_slice0_extent_sa() specific to * A variant of isl_calc_phys_slice0_extent_sa() specific to
* ISL_DIM_LAYOUT_GEN4_3D. * ISL_DIM_LAYOUT_GFX4_3D.
*/ */
static void static void
isl_calc_phys_total_extent_el_gfx4_3d( isl_calc_phys_total_extent_el_gfx4_3d(
@ -1260,7 +1260,7 @@ isl_calc_phys_total_extent_el_gfx4_3d(
/** /**
* A variant of isl_calc_phys_slice0_extent_sa() specific to * A variant of isl_calc_phys_slice0_extent_sa() specific to
* ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ. * ISL_DIM_LAYOUT_GFX6_STENCIL_HIZ.
*/ */
static void static void
isl_calc_phys_total_extent_el_gfx6_stencil_hiz( isl_calc_phys_total_extent_el_gfx6_stencil_hiz(
@ -1321,7 +1321,7 @@ isl_calc_phys_total_extent_el_gfx6_stencil_hiz(
/** /**
* A variant of isl_calc_phys_slice0_extent_sa() specific to * A variant of isl_calc_phys_slice0_extent_sa() specific to
* ISL_DIM_LAYOUT_GEN9_1D. * ISL_DIM_LAYOUT_GFX9_1D.
*/ */
static void static void
isl_calc_phys_total_extent_el_gfx9_1d( isl_calc_phys_total_extent_el_gfx9_1d(
@ -1373,21 +1373,21 @@ isl_calc_phys_total_extent_el(const struct isl_device *dev,
struct isl_extent2d *total_extent_el) struct isl_extent2d *total_extent_el)
{ {
switch (dim_layout) { switch (dim_layout) {
case ISL_DIM_LAYOUT_GEN9_1D: case ISL_DIM_LAYOUT_GFX9_1D:
assert(array_pitch_span == ISL_ARRAY_PITCH_SPAN_COMPACT); assert(array_pitch_span == ISL_ARRAY_PITCH_SPAN_COMPACT);
isl_calc_phys_total_extent_el_gfx9_1d(dev, info, isl_calc_phys_total_extent_el_gfx9_1d(dev, info,
image_align_sa, phys_level0_sa, image_align_sa, phys_level0_sa,
array_pitch_el_rows, array_pitch_el_rows,
total_extent_el); total_extent_el);
return; return;
case ISL_DIM_LAYOUT_GEN4_2D: case ISL_DIM_LAYOUT_GFX4_2D:
isl_calc_phys_total_extent_el_gfx4_2d(dev, info, tile_info, msaa_layout, isl_calc_phys_total_extent_el_gfx4_2d(dev, info, tile_info, msaa_layout,
image_align_sa, phys_level0_sa, image_align_sa, phys_level0_sa,
array_pitch_span, array_pitch_span,
array_pitch_el_rows, array_pitch_el_rows,
total_extent_el); total_extent_el);
return; return;
case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ: case ISL_DIM_LAYOUT_GFX6_STENCIL_HIZ:
assert(array_pitch_span == ISL_ARRAY_PITCH_SPAN_COMPACT); assert(array_pitch_span == ISL_ARRAY_PITCH_SPAN_COMPACT);
isl_calc_phys_total_extent_el_gfx6_stencil_hiz(dev, info, tile_info, isl_calc_phys_total_extent_el_gfx6_stencil_hiz(dev, info, tile_info,
image_align_sa, image_align_sa,
@ -1395,7 +1395,7 @@ isl_calc_phys_total_extent_el(const struct isl_device *dev,
array_pitch_el_rows, array_pitch_el_rows,
total_extent_el); total_extent_el);
return; return;
case ISL_DIM_LAYOUT_GEN4_3D: case ISL_DIM_LAYOUT_GFX4_3D:
assert(array_pitch_span == ISL_ARRAY_PITCH_SPAN_COMPACT); assert(array_pitch_span == ISL_ARRAY_PITCH_SPAN_COMPACT);
isl_calc_phys_total_extent_el_gfx4_3d(dev, info, isl_calc_phys_total_extent_el_gfx4_3d(dev, info,
image_align_sa, phys_level0_sa, image_align_sa, phys_level0_sa,
@ -1572,7 +1572,7 @@ isl_calc_row_pitch(const struct isl_device *dev,
if (row_pitch_B == 0) if (row_pitch_B == 0)
return false; return false;
if (dim_layout == ISL_DIM_LAYOUT_GEN9_1D) { if (dim_layout == ISL_DIM_LAYOUT_GFX9_1D) {
/* SurfacePitch is ignored for this layout. */ /* SurfacePitch is ignored for this layout. */
goto done; goto done;
} }
@ -1712,7 +1712,7 @@ isl_surf_init_s(const struct isl_device *dev,
* pages. We currently don't assign the usage field like we do for main * pages. We currently don't assign the usage field like we do for main
* surfaces, so just use 4K for now. * surfaces, so just use 4K for now.
*/ */
if (tiling == ISL_TILING_GEN12_CCS) if (tiling == ISL_TILING_GFX12_CCS)
base_alignment_B = MAX(base_alignment_B, 4096); base_alignment_B = MAX(base_alignment_B, 4096);
/* Gfx12+ requires that images be 64K-aligned if they're going to used /* Gfx12+ requires that images be 64K-aligned if they're going to used
@ -2118,11 +2118,11 @@ isl_surf_get_ccs_surf(const struct isl_device *dev,
if (ISL_GFX_VER(dev) >= 12) { if (ISL_GFX_VER(dev) >= 12) {
enum isl_format ccs_format; enum isl_format ccs_format;
switch (isl_format_get_layout(surf->format)->bpb) { switch (isl_format_get_layout(surf->format)->bpb) {
case 8: ccs_format = ISL_FORMAT_GEN12_CCS_8BPP_Y0; break; case 8: ccs_format = ISL_FORMAT_GFX12_CCS_8BPP_Y0; break;
case 16: ccs_format = ISL_FORMAT_GEN12_CCS_16BPP_Y0; break; case 16: ccs_format = ISL_FORMAT_GFX12_CCS_16BPP_Y0; break;
case 32: ccs_format = ISL_FORMAT_GEN12_CCS_32BPP_Y0; break; case 32: ccs_format = ISL_FORMAT_GFX12_CCS_32BPP_Y0; break;
case 64: ccs_format = ISL_FORMAT_GEN12_CCS_64BPP_Y0; break; case 64: ccs_format = ISL_FORMAT_GFX12_CCS_64BPP_Y0; break;
case 128: ccs_format = ISL_FORMAT_GEN12_CCS_128BPP_Y0; break; case 128: ccs_format = ISL_FORMAT_GFX12_CCS_128BPP_Y0; break;
default: default:
return false; return false;
} }
@ -2144,31 +2144,31 @@ isl_surf_get_ccs_surf(const struct isl_device *dev,
.samples = 1, .samples = 1,
.row_pitch_B = row_pitch_B, .row_pitch_B = row_pitch_B,
.usage = ISL_SURF_USAGE_CCS_BIT, .usage = ISL_SURF_USAGE_CCS_BIT,
.tiling_flags = ISL_TILING_GEN12_CCS_BIT); .tiling_flags = ISL_TILING_GFX12_CCS_BIT);
assert(!ok || ccs_surf->size_B == surf->size_B / 256); assert(!ok || ccs_surf->size_B == surf->size_B / 256);
return ok; return ok;
} else { } else {
enum isl_format ccs_format; enum isl_format ccs_format;
if (ISL_GFX_VER(dev) >= 9) { if (ISL_GFX_VER(dev) >= 9) {
switch (isl_format_get_layout(surf->format)->bpb) { switch (isl_format_get_layout(surf->format)->bpb) {
case 32: ccs_format = ISL_FORMAT_GEN9_CCS_32BPP; break; case 32: ccs_format = ISL_FORMAT_GFX9_CCS_32BPP; break;
case 64: ccs_format = ISL_FORMAT_GEN9_CCS_64BPP; break; case 64: ccs_format = ISL_FORMAT_GFX9_CCS_64BPP; break;
case 128: ccs_format = ISL_FORMAT_GEN9_CCS_128BPP; break; case 128: ccs_format = ISL_FORMAT_GFX9_CCS_128BPP; break;
default: unreachable("Unsupported CCS format"); default: unreachable("Unsupported CCS format");
return false; return false;
} }
} else if (surf->tiling == ISL_TILING_Y0) { } else if (surf->tiling == ISL_TILING_Y0) {
switch (isl_format_get_layout(surf->format)->bpb) { switch (isl_format_get_layout(surf->format)->bpb) {
case 32: ccs_format = ISL_FORMAT_GEN7_CCS_32BPP_Y; break; case 32: ccs_format = ISL_FORMAT_GFX7_CCS_32BPP_Y; break;
case 64: ccs_format = ISL_FORMAT_GEN7_CCS_64BPP_Y; break; case 64: ccs_format = ISL_FORMAT_GFX7_CCS_64BPP_Y; break;
case 128: ccs_format = ISL_FORMAT_GEN7_CCS_128BPP_Y; break; case 128: ccs_format = ISL_FORMAT_GFX7_CCS_128BPP_Y; break;
default: unreachable("Unsupported CCS format"); default: unreachable("Unsupported CCS format");
} }
} else if (surf->tiling == ISL_TILING_X) { } else if (surf->tiling == ISL_TILING_X) {
switch (isl_format_get_layout(surf->format)->bpb) { switch (isl_format_get_layout(surf->format)->bpb) {
case 32: ccs_format = ISL_FORMAT_GEN7_CCS_32BPP_X; break; case 32: ccs_format = ISL_FORMAT_GFX7_CCS_32BPP_X; break;
case 64: ccs_format = ISL_FORMAT_GEN7_CCS_64BPP_X; break; case 64: ccs_format = ISL_FORMAT_GFX7_CCS_64BPP_X; break;
case 128: ccs_format = ISL_FORMAT_GEN7_CCS_128BPP_X; break; case 128: ccs_format = ISL_FORMAT_GFX7_CCS_128BPP_X; break;
default: unreachable("Unsupported CCS format"); default: unreachable("Unsupported CCS format");
} }
} else { } else {
@ -2307,7 +2307,7 @@ isl_emit_depth_stencil_hiz_s(const struct isl_device *dev, void *batch,
/** /**
* A variant of isl_surf_get_image_offset_sa() specific to * A variant of isl_surf_get_image_offset_sa() specific to
* ISL_DIM_LAYOUT_GEN4_2D. * ISL_DIM_LAYOUT_GFX4_2D.
*/ */
static void static void
get_image_offset_sa_gfx4_2d(const struct isl_surf *surf, get_image_offset_sa_gfx4_2d(const struct isl_surf *surf,
@ -2349,7 +2349,7 @@ get_image_offset_sa_gfx4_2d(const struct isl_surf *surf,
/** /**
* A variant of isl_surf_get_image_offset_sa() specific to * A variant of isl_surf_get_image_offset_sa() specific to
* ISL_DIM_LAYOUT_GEN4_3D. * ISL_DIM_LAYOUT_GFX4_3D.
*/ */
static void static void
get_image_offset_sa_gfx4_3d(const struct isl_surf *surf, get_image_offset_sa_gfx4_3d(const struct isl_surf *surf,
@ -2465,7 +2465,7 @@ get_image_offset_sa_gfx6_stencil_hiz(const struct isl_surf *surf,
/** /**
* A variant of isl_surf_get_image_offset_sa() specific to * A variant of isl_surf_get_image_offset_sa() specific to
* ISL_DIM_LAYOUT_GEN9_1D. * ISL_DIM_LAYOUT_GFX9_1D.
*/ */
static void static void
get_image_offset_sa_gfx9_1d(const struct isl_surf *surf, get_image_offset_sa_gfx9_1d(const struct isl_surf *surf,
@ -2518,21 +2518,21 @@ isl_surf_get_image_offset_sa(const struct isl_surf *surf,
< isl_minify(surf->logical_level0_px.depth, level)); < isl_minify(surf->logical_level0_px.depth, level));
switch (surf->dim_layout) { switch (surf->dim_layout) {
case ISL_DIM_LAYOUT_GEN9_1D: case ISL_DIM_LAYOUT_GFX9_1D:
get_image_offset_sa_gfx9_1d(surf, level, logical_array_layer, get_image_offset_sa_gfx9_1d(surf, level, logical_array_layer,
x_offset_sa, y_offset_sa); x_offset_sa, y_offset_sa);
break; break;
case ISL_DIM_LAYOUT_GEN4_2D: case ISL_DIM_LAYOUT_GFX4_2D:
get_image_offset_sa_gfx4_2d(surf, level, logical_array_layer get_image_offset_sa_gfx4_2d(surf, level, logical_array_layer
+ logical_z_offset_px, + logical_z_offset_px,
x_offset_sa, y_offset_sa); x_offset_sa, y_offset_sa);
break; break;
case ISL_DIM_LAYOUT_GEN4_3D: case ISL_DIM_LAYOUT_GFX4_3D:
get_image_offset_sa_gfx4_3d(surf, level, logical_array_layer + get_image_offset_sa_gfx4_3d(surf, level, logical_array_layer +
logical_z_offset_px, logical_z_offset_px,
x_offset_sa, y_offset_sa); x_offset_sa, y_offset_sa);
break; break;
case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ: case ISL_DIM_LAYOUT_GFX6_STENCIL_HIZ:
get_image_offset_sa_gfx6_stencil_hiz(surf, level, logical_array_layer + get_image_offset_sa_gfx6_stencil_hiz(surf, level, logical_array_layer +
logical_z_offset_px, logical_z_offset_px,
x_offset_sa, y_offset_sa); x_offset_sa, y_offset_sa);

46
src/intel/isl/isl.h
View file

@ -388,20 +388,20 @@ enum isl_format {
ISL_FORMAT_MCS_4X, ISL_FORMAT_MCS_4X,
ISL_FORMAT_MCS_8X, ISL_FORMAT_MCS_8X,
ISL_FORMAT_MCS_16X, ISL_FORMAT_MCS_16X,
ISL_FORMAT_GEN7_CCS_32BPP_X, ISL_FORMAT_GFX7_CCS_32BPP_X,
ISL_FORMAT_GEN7_CCS_64BPP_X, ISL_FORMAT_GFX7_CCS_64BPP_X,
ISL_FORMAT_GEN7_CCS_128BPP_X, ISL_FORMAT_GFX7_CCS_128BPP_X,
ISL_FORMAT_GEN7_CCS_32BPP_Y, ISL_FORMAT_GFX7_CCS_32BPP_Y,
ISL_FORMAT_GEN7_CCS_64BPP_Y, ISL_FORMAT_GFX7_CCS_64BPP_Y,
ISL_FORMAT_GEN7_CCS_128BPP_Y, ISL_FORMAT_GFX7_CCS_128BPP_Y,
ISL_FORMAT_GEN9_CCS_32BPP, ISL_FORMAT_GFX9_CCS_32BPP,
ISL_FORMAT_GEN9_CCS_64BPP, ISL_FORMAT_GFX9_CCS_64BPP,
ISL_FORMAT_GEN9_CCS_128BPP, ISL_FORMAT_GFX9_CCS_128BPP,
ISL_FORMAT_GEN12_CCS_8BPP_Y0, ISL_FORMAT_GFX12_CCS_8BPP_Y0,
ISL_FORMAT_GEN12_CCS_16BPP_Y0, ISL_FORMAT_GFX12_CCS_16BPP_Y0,
ISL_FORMAT_GEN12_CCS_32BPP_Y0, ISL_FORMAT_GFX12_CCS_32BPP_Y0,
ISL_FORMAT_GEN12_CCS_64BPP_Y0, ISL_FORMAT_GFX12_CCS_64BPP_Y0,
ISL_FORMAT_GEN12_CCS_128BPP_Y0, ISL_FORMAT_GFX12_CCS_128BPP_Y0,
/* An upper bound on the supported format enumerations */ /* An upper bound on the supported format enumerations */
ISL_NUM_FORMATS, ISL_NUM_FORMATS,
@ -478,7 +478,7 @@ enum isl_tiling {
ISL_TILING_Ys, /**< Standard 64K tiling. The 's' means "sixty-four". */ ISL_TILING_Ys, /**< Standard 64K tiling. The 's' means "sixty-four". */
ISL_TILING_HIZ, /**< Tiling format for HiZ surfaces */ ISL_TILING_HIZ, /**< Tiling format for HiZ surfaces */
ISL_TILING_CCS, /**< Tiling format for CCS surfaces */ ISL_TILING_CCS, /**< Tiling format for CCS surfaces */
ISL_TILING_GEN12_CCS, /**< Tiling format for Gfx12 CCS surfaces */ ISL_TILING_GFX12_CCS, /**< Tiling format for Gfx12 CCS surfaces */
}; };
/** /**
@ -494,7 +494,7 @@ typedef uint32_t isl_tiling_flags_t;
#define ISL_TILING_Ys_BIT (1u << ISL_TILING_Ys) #define ISL_TILING_Ys_BIT (1u << ISL_TILING_Ys)
#define ISL_TILING_HIZ_BIT (1u << ISL_TILING_HIZ) #define ISL_TILING_HIZ_BIT (1u << ISL_TILING_HIZ)
#define ISL_TILING_CCS_BIT (1u << ISL_TILING_CCS) #define ISL_TILING_CCS_BIT (1u << ISL_TILING_CCS)
#define ISL_TILING_GEN12_CCS_BIT (1u << ISL_TILING_GEN12_CCS) #define ISL_TILING_GFX12_CCS_BIT (1u << ISL_TILING_GFX12_CCS)
#define ISL_TILING_ANY_MASK (~0u) #define ISL_TILING_ANY_MASK (~0u)
#define ISL_TILING_NON_LINEAR_MASK (~ISL_TILING_LINEAR_BIT) #define ISL_TILING_NON_LINEAR_MASK (~ISL_TILING_LINEAR_BIT)
@ -536,7 +536,7 @@ enum isl_dim_layout {
* *
* @invariant isl_surf::phys_level0_sa::depth == 1 * @invariant isl_surf::phys_level0_sa::depth == 1
*/ */
ISL_DIM_LAYOUT_GEN4_2D, ISL_DIM_LAYOUT_GFX4_2D,
/** /**
* For details, see the G35 PRM >> Volume 1: Graphics Core >> Section * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section
@ -544,7 +544,7 @@ enum isl_dim_layout {
* *
* @invariant isl_surf::phys_level0_sa::array_len == 1 * @invariant isl_surf::phys_level0_sa::array_len == 1
*/ */
ISL_DIM_LAYOUT_GEN4_3D, ISL_DIM_LAYOUT_GFX4_3D,
/** /**
* Special layout used for HiZ and stencil on Sandy Bridge to work around * Special layout used for HiZ and stencil on Sandy Bridge to work around
@ -584,13 +584,13 @@ enum isl_dim_layout {
* | | +-+ * | | +-+
* +----+ * +----+
*/ */
ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ, ISL_DIM_LAYOUT_GFX6_STENCIL_HIZ,
/** /**
* For details, see the Skylake BSpec >> Memory Views >> Common Surface * For details, see the Skylake BSpec >> Memory Views >> Common Surface
* Formats >> Surface Layout and Tiling >> » 1D Surfaces. * Formats >> Surface Layout and Tiling >> » 1D Surfaces.
*/ */
ISL_DIM_LAYOUT_GEN9_1D, ISL_DIM_LAYOUT_GFX9_1D,
}; };
enum isl_aux_usage { enum isl_aux_usage {
@ -623,7 +623,7 @@ enum isl_aux_usage {
* *
* @invariant isl_surf::samples == 1 * @invariant isl_surf::samples == 1
*/ */
ISL_AUX_USAGE_GEN12_CCS_E, ISL_AUX_USAGE_GFX12_CCS_E,
/** The auxiliary surface provides full lossless media color compression /** The auxiliary surface provides full lossless media color compression
* *
@ -1828,7 +1828,7 @@ isl_aux_usage_has_ccs(enum isl_aux_usage usage)
{ {
return usage == ISL_AUX_USAGE_CCS_D || return usage == ISL_AUX_USAGE_CCS_D ||
usage == ISL_AUX_USAGE_CCS_E || usage == ISL_AUX_USAGE_CCS_E ||
usage == ISL_AUX_USAGE_GEN12_CCS_E || usage == ISL_AUX_USAGE_GFX12_CCS_E ||
usage == ISL_AUX_USAGE_MC || usage == ISL_AUX_USAGE_MC ||
usage == ISL_AUX_USAGE_HIZ_CCS_WT || usage == ISL_AUX_USAGE_HIZ_CCS_WT ||
usage == ISL_AUX_USAGE_HIZ_CCS || usage == ISL_AUX_USAGE_HIZ_CCS ||
@ -1898,7 +1898,7 @@ isl_drm_modifier_get_default_aux_state(uint64_t modifier)
return ISL_AUX_STATE_AUX_INVALID; return ISL_AUX_STATE_AUX_INVALID;
assert(mod_info->aux_usage == ISL_AUX_USAGE_CCS_E || assert(mod_info->aux_usage == ISL_AUX_USAGE_CCS_E ||
mod_info->aux_usage == ISL_AUX_USAGE_GEN12_CCS_E || mod_info->aux_usage == ISL_AUX_USAGE_GFX12_CCS_E ||
mod_info->aux_usage == ISL_AUX_USAGE_MC); mod_info->aux_usage == ISL_AUX_USAGE_MC);
return mod_info->supports_clear_color ? ISL_AUX_STATE_COMPRESSED_CLEAR : return mod_info->supports_clear_color ? ISL_AUX_STATE_COMPRESSED_CLEAR :
ISL_AUX_STATE_COMPRESSED_NO_CLEAR; ISL_AUX_STATE_COMPRESSED_NO_CLEAR;

2
src/intel/isl/isl_aux_info.c
View file

@ -92,7 +92,7 @@ static const struct aux_usage_info info[] = {
AUX( COMPRESS, Y, Y, Y, x, MCS) AUX( COMPRESS, Y, Y, Y, x, MCS)
AUX( COMPRESS, Y, Y, Y, x, MCS_CCS) AUX( COMPRESS, Y, Y, Y, x, MCS_CCS)
AUX( COMPRESS, Y, Y, Y, Y, CCS_E) AUX( COMPRESS, Y, Y, Y, Y, CCS_E)
AUX( COMPRESS_CLEAR, Y, Y, Y, Y, GEN12_CCS_E) AUX( COMPRESS_CLEAR, Y, Y, Y, Y, GFX12_CCS_E)
AUX(RESOLVE_AMBIGUATE, x, Y, x, Y, CCS_D) AUX(RESOLVE_AMBIGUATE, x, Y, x, Y, CCS_D)
AUX(RESOLVE_AMBIGUATE, Y, x, x, Y, MC) AUX(RESOLVE_AMBIGUATE, Y, x, x, Y, MC)
AUX( COMPRESS, Y, x, x, Y, STC_CCS) AUX( COMPRESS, Y, x, x, Y, STC_CCS)

4
src/intel/isl/isl_drm.c
View file

@ -49,7 +49,7 @@ isl_tiling_to_i915_tiling(enum isl_tiling tiling)
case ISL_TILING_W: case ISL_TILING_W:
case ISL_TILING_Yf: case ISL_TILING_Yf:
case ISL_TILING_Ys: case ISL_TILING_Ys:
case ISL_TILING_GEN12_CCS: case ISL_TILING_GFX12_CCS:
return I915_TILING_NONE; return I915_TILING_NONE;
} }
@ -102,7 +102,7 @@ isl_drm_modifier_info_list[] = {
.modifier = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS, .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
.name = "I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS", .name = "I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS",
.tiling = ISL_TILING_Y0, .tiling = ISL_TILING_Y0,
.aux_usage = ISL_AUX_USAGE_GEN12_CCS_E, .aux_usage = ISL_AUX_USAGE_GFX12_CCS_E,
.supports_clear_color = false, .supports_clear_color = false,
}, },
{ {

28
src/intel/isl/isl_format_layout.csv
View file

@ -337,17 +337,17 @@ MCS_2X , 8, 1, 1, 1, , , , , ,
MCS_4X , 8, 1, 1, 1, , , , , , , , , , mcs MCS_4X , 8, 1, 1, 1, , , , , , , , , , mcs
MCS_8X , 32, 1, 1, 1, , , , , , , , , , mcs MCS_8X , 32, 1, 1, 1, , , , , , , , , , mcs
MCS_16X , 64, 1, 1, 1, , , , , , , , , , mcs MCS_16X , 64, 1, 1, 1, , , , , , , , , , mcs
GEN7_CCS_32BPP_X , 1, 16, 2, 1, , , , , , , , , , ccs GFX7_CCS_32BPP_X , 1, 16, 2, 1, , , , , , , , , , ccs
GEN7_CCS_64BPP_X , 1, 8, 2, 1, , , , , , , , , , ccs GFX7_CCS_64BPP_X , 1, 8, 2, 1, , , , , , , , , , ccs
GEN7_CCS_128BPP_X , 1, 4, 2, 1, , , , , , , , , , ccs GFX7_CCS_128BPP_X , 1, 4, 2, 1, , , , , , , , , , ccs
GEN7_CCS_32BPP_Y , 1, 8, 4, 1, , , , , , , , , , ccs GFX7_CCS_32BPP_Y , 1, 8, 4, 1, , , , , , , , , , ccs
GEN7_CCS_64BPP_Y , 1, 4, 4, 1, , , , , , , , , , ccs GFX7_CCS_64BPP_Y , 1, 4, 4, 1, , , , , , , , , , ccs
GEN7_CCS_128BPP_Y , 1, 2, 4, 1, , , , , , , , , , ccs GFX7_CCS_128BPP_Y , 1, 2, 4, 1, , , , , , , , , , ccs
GEN9_CCS_32BPP , 2, 8, 4, 1, , , , , , , , , , ccs GFX9_CCS_32BPP , 2, 8, 4, 1, , , , , , , , , , ccs
GEN9_CCS_64BPP , 2, 4, 4, 1, , , , , , , , , , ccs GFX9_CCS_64BPP , 2, 4, 4, 1, , , , , , , , , , ccs
GEN9_CCS_128BPP , 2, 2, 4, 1, , , , , , , , , , ccs GFX9_CCS_128BPP , 2, 2, 4, 1, , , , , , , , , , ccs
GEN12_CCS_8BPP_Y0 , 4, 32, 4, 1, , , , , , , , , , ccs GFX12_CCS_8BPP_Y0 , 4, 32, 4, 1, , , , , , , , , , ccs
GEN12_CCS_16BPP_Y0 , 4, 16, 4, 1, , , , , , , , , , ccs GFX12_CCS_16BPP_Y0 , 4, 16, 4, 1, , , , , , , , , , ccs
GEN12_CCS_32BPP_Y0 , 4, 8, 4, 1, , , , , , , , , , ccs GFX12_CCS_32BPP_Y0 , 4, 8, 4, 1, , , , , , , , , , ccs
GEN12_CCS_64BPP_Y0 , 4, 4, 4, 1, , , , , , , , , , ccs GFX12_CCS_64BPP_Y0 , 4, 4, 4, 1, , , , , , , , , , ccs
GEN12_CCS_128BPP_Y0 , 4, 2, 4, 1, , , , , , , , , , ccs GFX12_CCS_128BPP_Y0 , 4, 2, 4, 1, , , , , , , , , , ccs

Can't render this file because it contains an unexpected character in line 4 and column 65.

2
src/intel/isl/isl_gfx9.c
View file

@ -174,7 +174,7 @@ isl_gfx9_choose_image_alignment_el(const struct isl_device *dev,
return; return;
} }
if (dim_layout == ISL_DIM_LAYOUT_GEN9_1D) { if (dim_layout == ISL_DIM_LAYOUT_GFX9_1D) {
/* See the Skylake BSpec > Memory Views > Common Surface Formats > Surface /* See the Skylake BSpec > Memory Views > Common Surface Formats > Surface
* Layout and Tiling > 1D Surfaces > 1D Alignment Requirements. * Layout and Tiling > 1D Surfaces > 1D Alignment Requirements.
*/ */

16
src/intel/isl/isl_surface_state.c
View file

@ -91,7 +91,7 @@ static const uint32_t isl_to_gen_aux_mode[] = {
[ISL_AUX_USAGE_NONE] = AUX_NONE, [ISL_AUX_USAGE_NONE] = AUX_NONE,
[ISL_AUX_USAGE_MC] = AUX_NONE, [ISL_AUX_USAGE_MC] = AUX_NONE,
[ISL_AUX_USAGE_MCS] = AUX_CCS_E, [ISL_AUX_USAGE_MCS] = AUX_CCS_E,
[ISL_AUX_USAGE_GEN12_CCS_E] = AUX_CCS_E, [ISL_AUX_USAGE_GFX12_CCS_E] = AUX_CCS_E,
[ISL_AUX_USAGE_CCS_E] = AUX_CCS_E, [ISL_AUX_USAGE_CCS_E] = AUX_CCS_E,
[ISL_AUX_USAGE_HIZ_CCS_WT] = AUX_CCS_E, [ISL_AUX_USAGE_HIZ_CCS_WT] = AUX_CCS_E,
[ISL_AUX_USAGE_MCS_CCS] = AUX_MCS_LCE, [ISL_AUX_USAGE_MCS_CCS] = AUX_MCS_LCE,
@ -150,7 +150,7 @@ get_image_alignment(const struct isl_surf *surf)
{ {
if (GFX_VER >= 9) { if (GFX_VER >= 9) {
if (isl_tiling_is_std_y(surf->tiling) || if (isl_tiling_is_std_y(surf->tiling) ||
surf->dim_layout == ISL_DIM_LAYOUT_GEN9_1D) { surf->dim_layout == ISL_DIM_LAYOUT_GFX9_1D) {
/* The hardware ignores the alignment values. Anyway, the surface's /* The hardware ignores the alignment values. Anyway, the surface's
* true alignment is likely outside the enum range of HALIGN* and * true alignment is likely outside the enum range of HALIGN* and
* VALIGN*. * VALIGN*.
@ -184,7 +184,7 @@ get_qpitch(const struct isl_surf *surf)
switch (surf->dim_layout) { switch (surf->dim_layout) {
default: default:
unreachable("Bad isl_surf_dim"); unreachable("Bad isl_surf_dim");
case ISL_DIM_LAYOUT_GEN4_2D: case ISL_DIM_LAYOUT_GFX4_2D:
if (GFX_VER >= 9) { if (GFX_VER >= 9) {
if (surf->dim == ISL_SURF_DIM_3D && surf->tiling == ISL_TILING_W) { if (surf->dim == ISL_SURF_DIM_3D && surf->tiling == ISL_TILING_W) {
/* This is rather annoying and completely undocumented. It /* This is rather annoying and completely undocumented. It
@ -212,7 +212,7 @@ get_qpitch(const struct isl_surf *surf)
*/ */
return isl_surf_get_array_pitch_sa_rows(surf); return isl_surf_get_array_pitch_sa_rows(surf);
} }
case ISL_DIM_LAYOUT_GEN9_1D: case ISL_DIM_LAYOUT_GFX9_1D:
/* QPitch is usually expressed as rows of surface elements (where /* QPitch is usually expressed as rows of surface elements (where
* a surface element is an compression block or a single surface * a surface element is an compression block or a single surface
* sample). Skylake 1D is an outlier. * sample). Skylake 1D is an outlier.
@ -224,8 +224,8 @@ get_qpitch(const struct isl_surf *surf)
* slices. * slices.
*/ */
return isl_surf_get_array_pitch_el(surf); return isl_surf_get_array_pitch_el(surf);
case ISL_DIM_LAYOUT_GEN4_3D: case ISL_DIM_LAYOUT_GFX4_3D:
/* QPitch doesn't make sense for ISL_DIM_LAYOUT_GEN4_3D since it uses a /* QPitch doesn't make sense for ISL_DIM_LAYOUT_GFX4_3D since it uses a
* different pitch at each LOD. Also, the QPitch field is ignored for * different pitch at each LOD. Also, the QPitch field is ignored for
* these surfaces. From the Broadwell PRM documentation for QPitch: * these surfaces. From the Broadwell PRM documentation for QPitch:
* *
@ -476,7 +476,7 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
#endif #endif
#endif #endif
if (info->surf->dim_layout == ISL_DIM_LAYOUT_GEN9_1D) { if (info->surf->dim_layout == ISL_DIM_LAYOUT_GFX9_1D) {
/* For gfx9 1-D textures, surface pitch is ignored */ /* For gfx9 1-D textures, surface pitch is ignored */
s.SurfacePitch = 0; s.SurfacePitch = 0;
} else { } else {
@ -591,7 +591,7 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
if (GFX_VER >= 12) { if (GFX_VER >= 12) {
assert(info->aux_usage == ISL_AUX_USAGE_MCS || assert(info->aux_usage == ISL_AUX_USAGE_MCS ||
info->aux_usage == ISL_AUX_USAGE_CCS_E || info->aux_usage == ISL_AUX_USAGE_CCS_E ||
info->aux_usage == ISL_AUX_USAGE_GEN12_CCS_E || info->aux_usage == ISL_AUX_USAGE_GFX12_CCS_E ||
info->aux_usage == ISL_AUX_USAGE_MC || info->aux_usage == ISL_AUX_USAGE_MC ||
info->aux_usage == ISL_AUX_USAGE_HIZ_CCS_WT || info->aux_usage == ISL_AUX_USAGE_HIZ_CCS_WT ||
info->aux_usage == ISL_AUX_USAGE_MCS_CCS || info->aux_usage == ISL_AUX_USAGE_MCS_CCS ||

28
src/intel/isl/tests/isl_aux_info_test.cpp
View file

@ -377,20 +377,20 @@ TEST(StateTransitionWrite, WritesCompress) {
} }
TEST(StateTransitionWrite, WritesCompressClear) { TEST(StateTransitionWrite, WritesCompressClear) {
E(CLEAR, GEN12_CCS_E, false, COMPRESSED_CLEAR); E(CLEAR, GFX12_CCS_E, false, COMPRESSED_CLEAR);
E(CLEAR, GEN12_CCS_E, true, COMPRESSED_CLEAR); E(CLEAR, GFX12_CCS_E, true, COMPRESSED_CLEAR);
E(PARTIAL_CLEAR, GEN12_CCS_E, false, COMPRESSED_CLEAR); E(PARTIAL_CLEAR, GFX12_CCS_E, false, COMPRESSED_CLEAR);
E(PARTIAL_CLEAR, GEN12_CCS_E, true, COMPRESSED_CLEAR); E(PARTIAL_CLEAR, GFX12_CCS_E, true, COMPRESSED_CLEAR);
E(COMPRESSED_CLEAR, GEN12_CCS_E, false, COMPRESSED_CLEAR); E(COMPRESSED_CLEAR, GFX12_CCS_E, false, COMPRESSED_CLEAR);
E(COMPRESSED_CLEAR, GEN12_CCS_E, true, COMPRESSED_CLEAR); E(COMPRESSED_CLEAR, GFX12_CCS_E, true, COMPRESSED_CLEAR);
E(COMPRESSED_NO_CLEAR, GEN12_CCS_E, false, COMPRESSED_CLEAR); E(COMPRESSED_NO_CLEAR, GFX12_CCS_E, false, COMPRESSED_CLEAR);
E(COMPRESSED_NO_CLEAR, GEN12_CCS_E, true, COMPRESSED_CLEAR); E(COMPRESSED_NO_CLEAR, GFX12_CCS_E, true, COMPRESSED_CLEAR);
E(RESOLVED, GEN12_CCS_E, false, COMPRESSED_CLEAR); E(RESOLVED, GFX12_CCS_E, false, COMPRESSED_CLEAR);
E(RESOLVED, GEN12_CCS_E, true, COMPRESSED_CLEAR); E(RESOLVED, GFX12_CCS_E, true, COMPRESSED_CLEAR);
E(PASS_THROUGH, GEN12_CCS_E, false, COMPRESSED_CLEAR); E(PASS_THROUGH, GFX12_CCS_E, false, COMPRESSED_CLEAR);
E(PASS_THROUGH, GEN12_CCS_E, true, COMPRESSED_CLEAR); E(PASS_THROUGH, GFX12_CCS_E, true, COMPRESSED_CLEAR);
E(AUX_INVALID, GEN12_CCS_E, false, ASSERT); E(AUX_INVALID, GFX12_CCS_E, false, ASSERT);
E(AUX_INVALID, GEN12_CCS_E, true, ASSERT); E(AUX_INVALID, GFX12_CCS_E, true, ASSERT);
} }
TEST(StateTransitionWrite, WritesResolveAmbiguate) { TEST(StateTransitionWrite, WritesResolveAmbiguate) {

2
src/intel/vulkan/anv_allocator.c
View file

@ -1645,7 +1645,7 @@ anv_device_alloc_bo(struct anv_device *device,
size = align_u64(size, 64 * 1024); size = align_u64(size, 64 * 1024);
/* See anv_bo::_ccs_size */ /* See anv_bo::_ccs_size */
ccs_size = align_u64(DIV_ROUND_UP(size, INTEL_AUX_MAP_GEN12_CCS_SCALE), 4096); ccs_size = align_u64(DIV_ROUND_UP(size, INTEL_AUX_MAP_GFX12_CCS_SCALE), 4096);
} }
uint32_t gem_handle = anv_gem_create(device, size + ccs_size); uint32_t gem_handle = anv_gem_create(device, size + ccs_size);

4
src/mesa/drivers/dri/i965/brw_context.h
View file

@ -211,7 +211,7 @@ enum brw_state_id {
BRW_STATE_PUSH_CONSTANT_ALLOCATION, BRW_STATE_PUSH_CONSTANT_ALLOCATION,
BRW_STATE_NUM_SAMPLES, BRW_STATE_NUM_SAMPLES,
BRW_STATE_TEXTURE_BUFFER, BRW_STATE_TEXTURE_BUFFER,
BRW_STATE_GEN4_UNIT_STATE, BRW_STATE_GFX4_UNIT_STATE,
BRW_STATE_CC_VP, BRW_STATE_CC_VP,
BRW_STATE_SF_VP, BRW_STATE_SF_VP,
BRW_STATE_CLIP_VP, BRW_STATE_CLIP_VP,
@ -303,7 +303,7 @@ enum brw_state_id {
#define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1ull << BRW_STATE_PUSH_CONSTANT_ALLOCATION) #define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1ull << BRW_STATE_PUSH_CONSTANT_ALLOCATION)
#define BRW_NEW_NUM_SAMPLES (1ull << BRW_STATE_NUM_SAMPLES) #define BRW_NEW_NUM_SAMPLES (1ull << BRW_STATE_NUM_SAMPLES)
#define BRW_NEW_TEXTURE_BUFFER (1ull << BRW_STATE_TEXTURE_BUFFER) #define BRW_NEW_TEXTURE_BUFFER (1ull << BRW_STATE_TEXTURE_BUFFER)
#define BRW_NEW_GEN4_UNIT_STATE (1ull << BRW_STATE_GEN4_UNIT_STATE) #define BRW_NEW_GFX4_UNIT_STATE (1ull << BRW_STATE_GFX4_UNIT_STATE)
#define BRW_NEW_CC_VP (1ull << BRW_STATE_CC_VP) #define BRW_NEW_CC_VP (1ull << BRW_STATE_CC_VP)
#define BRW_NEW_SF_VP (1ull << BRW_STATE_SF_VP) #define BRW_NEW_SF_VP (1ull << BRW_STATE_SF_VP)
#define BRW_NEW_CLIP_VP (1ull << BRW_STATE_CLIP_VP) #define BRW_NEW_CLIP_VP (1ull << BRW_STATE_CLIP_VP)

2
src/mesa/drivers/dri/i965/brw_ff_gs_emit.c
View file

@ -453,7 +453,7 @@ gfx6_sol_program(struct brw_ff_gs_compile *c, struct brw_ff_gs_prog_key *key,
final_write ? c->reg.temp : brw_null_reg(), /* dest */ final_write ? c->reg.temp : brw_null_reg(), /* dest */
1, /* msg_reg_nr */ 1, /* msg_reg_nr */
c->reg.header, /* src0 */ c->reg.header, /* src0 */
BRW_GEN6_SOL_BINDING_START + binding, /* binding_table_index */ BRW_GFX6_SOL_BINDING_START + binding, /* binding_table_index */
final_write); /* send_commit_msg */ final_write); /* send_commit_msg */
} }
} }

14
src/mesa/drivers/dri/i965/brw_mipmap_tree.c
View file

@ -247,7 +247,7 @@ get_num_phys_layers(const struct isl_surf *surf, unsigned level)
if (surf->dim != ISL_SURF_DIM_3D) if (surf->dim != ISL_SURF_DIM_3D)
return surf->phys_level0_sa.array_len; return surf->phys_level0_sa.array_len;
if (surf->dim_layout == ISL_DIM_LAYOUT_GEN4_2D) if (surf->dim_layout == ISL_DIM_LAYOUT_GFX4_2D)
return minify(surf->phys_level0_sa.array_len, level); return minify(surf->phys_level0_sa.array_len, level);
return minify(surf->phys_level0_sa.depth, level); return minify(surf->phys_level0_sa.depth, level);
@ -2298,7 +2298,7 @@ brw_update_r8stencil(struct brw_context *brw,
assert(src->surf.size_B > 0); assert(src->surf.size_B > 0);
if (!mt->shadow_mt) { if (!mt->shadow_mt) {
assert(devinfo->ver > 6); /* Handle MIPTREE_LAYOUT_GEN6_HIZ_STENCIL */ assert(devinfo->ver > 6); /* Handle MIPTREE_LAYOUT_GFX6_HIZ_STENCIL */
mt->shadow_mt = make_surface( mt->shadow_mt = make_surface(
brw, brw,
src->target, src->target,
@ -3170,7 +3170,7 @@ get_isl_dim_layout(const struct gen_device_info *devinfo,
case GL_TEXTURE_1D: case GL_TEXTURE_1D:
case GL_TEXTURE_1D_ARRAY: case GL_TEXTURE_1D_ARRAY:
return (devinfo->ver >= 9 && tiling == ISL_TILING_LINEAR ? return (devinfo->ver >= 9 && tiling == ISL_TILING_LINEAR ?
ISL_DIM_LAYOUT_GEN9_1D : ISL_DIM_LAYOUT_GEN4_2D); ISL_DIM_LAYOUT_GFX9_1D : ISL_DIM_LAYOUT_GFX4_2D);
case GL_TEXTURE_2D: case GL_TEXTURE_2D:
case GL_TEXTURE_2D_ARRAY: case GL_TEXTURE_2D_ARRAY:
@ -3178,16 +3178,16 @@ get_isl_dim_layout(const struct gen_device_info *devinfo,
case GL_TEXTURE_2D_MULTISAMPLE: case GL_TEXTURE_2D_MULTISAMPLE:
case GL_TEXTURE_2D_MULTISAMPLE_ARRAY: case GL_TEXTURE_2D_MULTISAMPLE_ARRAY:
case GL_TEXTURE_EXTERNAL_OES: case GL_TEXTURE_EXTERNAL_OES:
return ISL_DIM_LAYOUT_GEN4_2D; return ISL_DIM_LAYOUT_GFX4_2D;
case GL_TEXTURE_CUBE_MAP: case GL_TEXTURE_CUBE_MAP:
case GL_TEXTURE_CUBE_MAP_ARRAY: case GL_TEXTURE_CUBE_MAP_ARRAY:
return (devinfo->ver == 4 ? ISL_DIM_LAYOUT_GEN4_3D : return (devinfo->ver == 4 ? ISL_DIM_LAYOUT_GFX4_3D :
ISL_DIM_LAYOUT_GEN4_2D); ISL_DIM_LAYOUT_GFX4_2D);
case GL_TEXTURE_3D: case GL_TEXTURE_3D:
return (devinfo->ver >= 9 ? return (devinfo->ver >= 9 ?
ISL_DIM_LAYOUT_GEN4_2D : ISL_DIM_LAYOUT_GEN4_3D); ISL_DIM_LAYOUT_GFX4_2D : ISL_DIM_LAYOUT_GFX4_3D);
} }
unreachable("Invalid texture target"); unreachable("Invalid texture target");

2
src/mesa/drivers/dri/i965/brw_misc_state.c
View file

@ -93,7 +93,7 @@ const struct brw_tracked_state brw_psp_urb_cbs = {
.brw = BRW_NEW_BATCH | .brw = BRW_NEW_BATCH |
BRW_NEW_BLORP | BRW_NEW_BLORP |
BRW_NEW_FF_GS_PROG_DATA | BRW_NEW_FF_GS_PROG_DATA |
BRW_NEW_GEN4_UNIT_STATE | BRW_NEW_GFX4_UNIT_STATE |
BRW_NEW_STATE_BASE_ADDRESS | BRW_NEW_STATE_BASE_ADDRESS |
BRW_NEW_URB_FENCE, BRW_NEW_URB_FENCE,
}, },

2
src/mesa/drivers/dri/i965/brw_state_upload.c
View file

@ -472,7 +472,7 @@ static struct dirty_bit_map brw_bits[] = {
DEFINE_BIT(BRW_NEW_PUSH_CONSTANT_ALLOCATION), DEFINE_BIT(BRW_NEW_PUSH_CONSTANT_ALLOCATION),
DEFINE_BIT(BRW_NEW_NUM_SAMPLES), DEFINE_BIT(BRW_NEW_NUM_SAMPLES),
DEFINE_BIT(BRW_NEW_TEXTURE_BUFFER), DEFINE_BIT(BRW_NEW_TEXTURE_BUFFER),
DEFINE_BIT(BRW_NEW_GEN4_UNIT_STATE), DEFINE_BIT(BRW_NEW_GFX4_UNIT_STATE),
DEFINE_BIT(BRW_NEW_CC_VP), DEFINE_BIT(BRW_NEW_CC_VP),
DEFINE_BIT(BRW_NEW_SF_VP), DEFINE_BIT(BRW_NEW_SF_VP),
DEFINE_BIT(BRW_NEW_CLIP_VP), DEFINE_BIT(BRW_NEW_CLIP_VP),

12
src/mesa/drivers/dri/i965/genX_state_upload.c
View file

@ -1281,7 +1281,7 @@ genX(upload_clip_state)(struct brw_context *brw)
{ {
struct gl_context *ctx = &brw->ctx; struct gl_context *ctx = &brw->ctx;
ctx->NewDriverState |= BRW_NEW_GEN4_UNIT_STATE; ctx->NewDriverState |= BRW_NEW_GFX4_UNIT_STATE;
brw_state_emit(brw, GENX(CLIP_STATE), 32, &brw->clip.state_offset, clip) { brw_state_emit(brw, GENX(CLIP_STATE), 32, &brw->clip.state_offset, clip) {
clip.KernelStartPointer = KSP(brw, brw->clip.prog_offset); clip.KernelStartPointer = KSP(brw, brw->clip.prog_offset);
clip.GRFRegisterCount = clip.GRFRegisterCount =
@ -1522,7 +1522,7 @@ genX(upload_sf)(struct brw_context *brw)
#if GFX_VER < 6 #if GFX_VER < 6
const struct brw_sf_prog_data *sf_prog_data = brw->sf.prog_data; const struct brw_sf_prog_data *sf_prog_data = brw->sf.prog_data;
ctx->NewDriverState |= BRW_NEW_GEN4_UNIT_STATE; ctx->NewDriverState |= BRW_NEW_GFX4_UNIT_STATE;
brw_state_emit(brw, GENX(SF_STATE), 64, &brw->sf.state_offset, sf) { brw_state_emit(brw, GENX(SF_STATE), 64, &brw->sf.state_offset, sf) {
sf.KernelStartPointer = KSP(brw, brw->sf.prog_offset); sf.KernelStartPointer = KSP(brw, brw->sf.prog_offset);
@ -1819,7 +1819,7 @@ genX(upload_wm)(struct brw_context *brw)
#if GFX_VER >= 6 #if GFX_VER >= 6
brw_batch_emit(brw, GENX(3DSTATE_WM), wm) { brw_batch_emit(brw, GENX(3DSTATE_WM), wm) {
#else #else
ctx->NewDriverState |= BRW_NEW_GEN4_UNIT_STATE; ctx->NewDriverState |= BRW_NEW_GFX4_UNIT_STATE;
brw_state_emit(brw, GENX(WM_STATE), 64, &stage_state->state_offset, wm) { brw_state_emit(brw, GENX(WM_STATE), 64, &stage_state->state_offset, wm) {
#endif #endif
@ -2161,7 +2161,7 @@ genX(upload_vs_state)(struct brw_context *brw)
#if GFX_VER >= 6 #if GFX_VER >= 6
brw_batch_emit(brw, GENX(3DSTATE_VS), vs) { brw_batch_emit(brw, GENX(3DSTATE_VS), vs) {
#else #else
ctx->NewDriverState |= BRW_NEW_GEN4_UNIT_STATE; ctx->NewDriverState |= BRW_NEW_GFX4_UNIT_STATE;
brw_state_emit(brw, GENX(VS_STATE), 32, &stage_state->state_offset, vs) { brw_state_emit(brw, GENX(VS_STATE), 32, &stage_state->state_offset, vs) {
#endif #endif
INIT_THREAD_DISPATCH_FIELDS(vs, Vertex); INIT_THREAD_DISPATCH_FIELDS(vs, Vertex);
@ -2599,7 +2599,7 @@ genX(upload_gs_state)(struct brw_context *brw)
#if GFX_VER >= 6 #if GFX_VER >= 6
brw_batch_emit(brw, GENX(3DSTATE_GS), gs) { brw_batch_emit(brw, GENX(3DSTATE_GS), gs) {
#else #else
ctx->NewDriverState |= BRW_NEW_GEN4_UNIT_STATE; ctx->NewDriverState |= BRW_NEW_GFX4_UNIT_STATE;
brw_state_emit(brw, GENX(GS_STATE), 32, &brw->ff_gs.state_offset, gs) { brw_state_emit(brw, GENX(GS_STATE), 32, &brw->ff_gs.state_offset, gs) {
#endif #endif
@ -3407,7 +3407,7 @@ genX(upload_color_calc_state)(struct brw_context *brw)
#endif #endif
} }
#else #else
brw->ctx.NewDriverState |= BRW_NEW_GEN4_UNIT_STATE; brw->ctx.NewDriverState |= BRW_NEW_GFX4_UNIT_STATE;
#endif #endif
} }

2
src/mesa/drivers/dri/i965/gfx6_sol.c
View file

@ -50,7 +50,7 @@ gfx6_update_sol_surfaces(struct brw_context *brw)
} }
for (int i = 0; i < BRW_MAX_SOL_BINDINGS; ++i) { for (int i = 0; i < BRW_MAX_SOL_BINDINGS; ++i) {
const int surf_index = BRW_GEN6_SOL_BINDING_START + i; const int surf_index = BRW_GFX6_SOL_BINDING_START + i;
if (xfb_active && i < linked_xfb_info->NumOutputs) { if (xfb_active && i < linked_xfb_info->NumOutputs) {
unsigned buffer = linked_xfb_info->Outputs[i].OutputBuffer; unsigned buffer = linked_xfb_info->Outputs[i].OutputBuffer;
unsigned buffer_offset = unsigned buffer_offset =