From e7ddddc9892810b65bda232a00f798aa4a258fc8 Mon Sep 17 00:00:00 2001 From: Jason Ekstrand Date: Mon, 23 Oct 2017 14:25:44 -0700 Subject: [PATCH] i965/miptree: Take an isl_format in render_aux_usage Not all rendering matches the miptree format. We allow rendering to texture views so there are cases where it may not match. In those cases, our current scheme of just passing the value of ctx->sRGBEnabled isn't viable. Instead, just do what we do for texturing and pass the view format in directly. Reviewed-by: Topi Pohjolainen Cc: mesa-stable@lists.freedesktop.org (cherry picked from commit 39c5c12f8fbee9eec26a627f247d1f3ef7d4bf39) [Andres Gomez: remove code which was trivially modified previously] Signed-off-by: Andres Gomez Conflicts: src/mesa/drivers/dri/i965/brw_draw.c src/mesa/drivers/dri/i965/brw_wm_surface_state.c --- src/mesa/drivers/dri/i965/brw_blorp.c | 8 +++---- src/mesa/drivers/dri/i965/brw_draw.c | 13 +++++++++-- .../drivers/dri/i965/brw_wm_surface_state.c | 17 ++++++-------- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 23 +++++++++---------- src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 9 +++++--- 5 files changed, 39 insertions(+), 31 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c index 9295cdeb099..447a14a6fe6 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp.c +++ b/src/mesa/drivers/dri/i965/brw_blorp.c @@ -327,7 +327,7 @@ brw_blorp_blit_miptrees(struct brw_context *brw, enum isl_format dst_isl_format = brw_blorp_to_isl_format(brw, dst_format, true); enum isl_aux_usage dst_aux_usage = - intel_miptree_render_aux_usage(brw, dst_mt, encode_srgb, false); + intel_miptree_render_aux_usage(brw, dst_mt, dst_isl_format, false); const bool dst_clear_supported = dst_aux_usage != ISL_AUX_USAGE_NONE; intel_miptree_prepare_access(brw, dst_mt, dst_level, 1, dst_layer, 1, dst_aux_usage, dst_clear_supported); @@ -892,9 +892,9 @@ do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb, irb->mt, irb->mt_level, irb->mt_layer, num_layers); enum isl_aux_usage aux_usage = - intel_miptree_render_aux_usage(brw, irb->mt, encode_srgb, false); + intel_miptree_render_aux_usage(brw, irb->mt, isl_format, false); intel_miptree_prepare_render(brw, irb->mt, level, irb->mt_layer, - num_layers, encode_srgb, false); + num_layers, isl_format, false); struct isl_surf isl_tmp[2]; struct blorp_surf surf; @@ -913,7 +913,7 @@ do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb, blorp_batch_finish(&batch); intel_miptree_finish_render(brw, irb->mt, level, irb->mt_layer, - num_layers, encode_srgb, false); + num_layers, isl_format, false); } return; diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c index d73a3dc827a..7d66c63263d 100644 --- a/src/mesa/drivers/dri/i965/brw_draw.c +++ b/src/mesa/drivers/dri/i965/brw_draw.c @@ -25,6 +25,7 @@ #include +#include "main/blend.h" #include "main/context.h" #include "main/condrender.h" #include "main/samplerobj.h" @@ -471,9 +472,13 @@ brw_predraw_resolve_framebuffer(struct brw_context *brw) if (irb == NULL || irb->mt == NULL) continue; + mesa_format mesa_format = + _mesa_get_render_format(ctx, intel_rb_format(irb)); + enum isl_format isl_format = brw_isl_format_for_mesa_format(mesa_format); + intel_miptree_prepare_render(brw, irb->mt, irb->mt_level, irb->mt_layer, irb->layer_count, - ctx->Color.sRGBEnabled, + isl_format, ctx->Color.BlendEnabled & (1 << i)); } } @@ -539,10 +544,14 @@ brw_postdraw_set_buffers_need_resolve(struct brw_context *brw) if (!irb) continue; + mesa_format mesa_format = + _mesa_get_render_format(ctx, intel_rb_format(irb)); + enum isl_format isl_format = brw_isl_format_for_mesa_format(mesa_format); + brw_render_cache_set_add_bo(brw, irb->mt->bo); intel_miptree_finish_render(brw, irb->mt, irb->mt_level, irb->mt_layer, irb->layer_count, - ctx->Color.sRGBEnabled, + isl_format, ctx->Color.BlendEnabled & (1 << i)); } } diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index 17e760c3295..79a13ebc5dc 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -215,15 +215,6 @@ brw_update_renderbuffer_surface(struct brw_context *brw, struct intel_renderbuffer *irb = intel_renderbuffer(rb); struct intel_mipmap_tree *mt = irb->mt; - enum isl_aux_usage aux_usage = - intel_miptree_render_aux_usage(brw, mt, ctx->Color.sRGBEnabled, - ctx->Color.BlendEnabled & (1 << unit)); - - if (flags & INTEL_AUX_BUFFER_DISABLED) { - assert(brw->gen >= 9); - aux_usage = ISL_AUX_USAGE_NONE; - } - assert(brw_render_target_supported(brw, rb)); mesa_format rb_format = _mesa_get_render_format(ctx, intel_rb_format(irb)); @@ -231,9 +222,15 @@ brw_update_renderbuffer_surface(struct brw_context *brw, _mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n", __func__, _mesa_get_format_name(rb_format)); } + enum isl_format isl_format = brw->mesa_to_isl_render_format[rb_format]; + + enum isl_aux_usage aux_usage = + brw->draw_aux_buffer_disabled[unit] ? ISL_AUX_USAGE_NONE : + intel_miptree_render_aux_usage(brw, mt, isl_format, + ctx->Color.BlendEnabled & (1 << unit)); struct isl_view view = { - .format = brw->mesa_to_isl_render_format[rb_format], + .format = isl_format, .base_level = irb->mt_level - irb->mt->first_level, .levels = 1, .base_array_layer = irb->mt_layer, diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index 06acc41bf56..3f703752e95 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c @@ -2570,7 +2570,8 @@ intel_miptree_prepare_fb_fetch(struct brw_context *brw, enum isl_aux_usage intel_miptree_render_aux_usage(struct brw_context *brw, struct intel_mipmap_tree *mt, - bool srgb_enabled, bool blend_enabled) + enum isl_format render_format, + bool blend_enabled) { switch (mt->aux_usage) { case ISL_AUX_USAGE_MCS: @@ -2581,12 +2582,8 @@ intel_miptree_render_aux_usage(struct brw_context *brw, return mt->mcs_buf ? ISL_AUX_USAGE_CCS_D : ISL_AUX_USAGE_NONE; case ISL_AUX_USAGE_CCS_E: { - mesa_format mesa_format = - srgb_enabled ? mt->format :_mesa_get_srgb_format_linear(mt->format); - enum isl_format isl_format = brw_isl_format_for_mesa_format(mesa_format); - /* If the format supports CCS_E, then we can just use it */ - if (isl_format_supports_ccs_e(&brw->screen->devinfo, isl_format)) + if (isl_format_supports_ccs_e(&brw->screen->devinfo, render_format)) return ISL_AUX_USAGE_CCS_E; /* Otherwise, we have to fall back to CCS_D */ @@ -2595,8 +2592,8 @@ intel_miptree_render_aux_usage(struct brw_context *brw, * formats. However, there are issues with blending where it doesn't * properly apply the sRGB curve to the clear color when blending. */ - if (blend_enabled && isl_format_is_srgb(isl_format) && - !isl_color_value_is_zero_one(mt->fast_clear_color, isl_format)) + if (blend_enabled && isl_format_is_srgb(render_format) && + !isl_color_value_is_zero_one(mt->fast_clear_color, render_format)) return ISL_AUX_USAGE_NONE; return ISL_AUX_USAGE_CCS_D; @@ -2611,10 +2608,11 @@ void intel_miptree_prepare_render(struct brw_context *brw, struct intel_mipmap_tree *mt, uint32_t level, uint32_t start_layer, uint32_t layer_count, - bool srgb_enabled, bool blend_enabled) + enum isl_format render_format, + bool blend_enabled) { enum isl_aux_usage aux_usage = - intel_miptree_render_aux_usage(brw, mt, srgb_enabled, blend_enabled); + intel_miptree_render_aux_usage(brw, mt, render_format, blend_enabled); intel_miptree_prepare_access(brw, mt, level, 1, start_layer, layer_count, aux_usage, aux_usage != ISL_AUX_USAGE_NONE); } @@ -2623,12 +2621,13 @@ void intel_miptree_finish_render(struct brw_context *brw, struct intel_mipmap_tree *mt, uint32_t level, uint32_t start_layer, uint32_t layer_count, - bool srgb_enabled, bool blend_enabled) + enum isl_format render_format, + bool blend_enabled) { assert(_mesa_is_format_color_format(mt->format)); enum isl_aux_usage aux_usage = - intel_miptree_render_aux_usage(brw, mt, srgb_enabled, blend_enabled); + intel_miptree_render_aux_usage(brw, mt, render_format, blend_enabled); intel_miptree_finish_write(brw, mt, level, start_layer, layer_count, aux_usage); } diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h index 9345daf669a..5f5110bb923 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h @@ -640,17 +640,20 @@ intel_miptree_prepare_fb_fetch(struct brw_context *brw, enum isl_aux_usage intel_miptree_render_aux_usage(struct brw_context *brw, struct intel_mipmap_tree *mt, - bool srgb_enabled, bool blend_enabled); + enum isl_format render_format, + bool blend_enabled); void intel_miptree_prepare_render(struct brw_context *brw, struct intel_mipmap_tree *mt, uint32_t level, uint32_t start_layer, uint32_t layer_count, - bool srgb_enabled, bool blend_enabled); + enum isl_format render_format, + bool blend_enabled); void intel_miptree_finish_render(struct brw_context *brw, struct intel_mipmap_tree *mt, uint32_t level, uint32_t start_layer, uint32_t layer_count, - bool srgb_enabled, bool blend_enabled); + enum isl_format render_format, + bool blend_enabled); void intel_miptree_prepare_depth(struct brw_context *brw, struct intel_mipmap_tree *mt, uint32_t level,